3D-IC Requires Expanded Power Grid Analysis


At advanced nodes, effective power grid analysis is critical to ensure that the small dimension interconnects can handle current demands without introducing potential failure modes or signal integrity issues. Existing software tools for power analysis need to be extended and enhanced for 2.5D and 3D designs to fulfill new requirements and use models. This article describes some of the needed improvements.

3D Requires System-Level Power Analysis
In a 3D-IC system several die share the same network supplies. The power grid analysis (PGA) tool must concurrently analyze all the dies, since the voltage drop for one could be directly linked to another. Also, PGA solutions must support various 2.5D/3D die configurations – accounting for placement, orientation, and stacking order – as well as models for inter-die interconnects.

Figure 1. PGA for 3D-IC must address the power characteristics of the entire packaged system, including multiple dies, interconnects, and interposer.

Each die in a system may have been targeted for a different process, depending on its application and requirements. A system could contain die designed at 40nm and 28nm, and an interposer designed at 65nm. Incremental technology file definition and calibration is important in this use case because end users need only calibrate the new part of a stack definition related to the 2.5D/3D integration, rather than re-calibrating the entire stack.

A PGA tool for 2.5D/3D flows must also take account the additional ‘objects’ required for vertical integration, such as backside bumps and backside metal layers (Figure 2). The backside metal layers in a 3D structure are routed at 45 degree angles instead of the usual 90 degrees used for front-side metal layers, which will affect the power analysis models. For full 3D, the PGA tools needs accurate models for through-silicon vias (TSVs) between front and backside metals, while for 2.5D systems PGA tools must be able to model passive interposers that contain only metal (no devices underneath).

Figure 2. PGA for 3D-IC stacks requires models for 3D integration objects such as through silicon vias (TSVs), backside bumps and metal layers.

Multiple Use Models for 3D Power Grid Analysis
Due to the typical size of 2.5D and 3D systems, and need to integrate third-party die, PGA solutions must be capable of running in three different modes.

  • Power model-based power grid analysis mode–In the power model-based mode, each die is represented by its compact power model, and the PGA tool analyzes the full 2.5D/3D IC system using the models and their connections. This mode runs fairly quickly to provide a high-level PGA of the system, but it is limited to detecting issues with the inter-die connections. Since power models are generated for technology node-specific corners, a PGA solution must be able to handle different compact power models for different corners. For instance, a 90nm die model for a 1.2V corner, combined with a 65nm die model for a 1.0V corner.
  • Full 2.5D/3D power grid analysis mode– End users want to analyze the voltage drop on specific multi-die nets, but this is computationally expensive. To enable this mode, the PGA tool’s capacity and turnaround time must be several orders of magnitude better than existing tools.
  • Hybrid power grid analysis mode–The hybrid mode is driven by the need to analyze third-party die integration. It enables a mix of compact power models and dies, where a third-party die is only represented by its compact model for integration into the system PGA.

Figure 3. PGA tools for 3D-IC must be able to support a hybrid mode that enables a mix of customer power models with third-party compact models.

Requirements for PGA Tools in the Design Flow
To detect, diagnose and correct power grid issues early and efficiently, designers should run PGA during floor planning, post-clock tree synthesis, and post-route implementation stages. To provide a meaningful analysis, the effects of the system on a given die (i.e., other die, interposer, 3D-IC integration objects, etc.) must be taken into account, and users should be able to analyze system interactions easily. Multi-frame capability and die-to-die browsing in a given stack allows users to review, diagnose and debug power grid issues efficiently. These capabilities require the tool to have significantly larger data capacity and faster response time, but these features are particularly important for debugging a dynamic PGA run.

Power Analysis Output Requirements
A PGA solution generates a power model of the full system that can be used for packaging/board power integrity analysis. The ability to do partial model generation is also important to enable third-party IP integration. For instance, if a supplier is analyzing a die on an interposer that will be connected to another die by customers, the supplier needs to deliver both a power model for the first die and the parasitics net list for the interposer.

Power grid analysis for 2.5D/3D ICs requires capabilities well beyond today’s PGA tools. Power is one of the biggest challenges in 2.5D/3D IC physical implementation, and issues that arise here cannot be solved at the RTL level only. To enable the semiconductor industry to fully embrace 3D integrations beyond just 2.5D, memory stack, and wide IO applications, PGA solutions must address the requirements discussed here, especially if the goal is to have a true 3D- IC integration flow with robust multi-die power grid floor planning capability.

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