Coverage-Driven Verification Isn’t Complete Without Low-Power Metrics

Native low power simulation is inherent in today’s advanced simulation environments to understand power design intent.


Coverage-driven verification enables the structured, measurable and manageable verification of today’s extraordinarily large and complex SoCs. Establishing predetermined objectives and planning for verification tasks is crucial to achieving closure on overall goals, and creating the comprehensive set of metrics to track during the verification process enables schedule predictability and confidence. As Peter Drucker says, “What gets measured, gets done”—planning is a crucial tool in helping to ensure chips get out the door on time.

The benefit of coverage-driven verification is dependent on the quality and completeness of the coverage metrics used in constrained-random verification methodologies. The general categories of code, functional and assertion coverage are well understood and new metrics, including those for static and formal checks, are becoming increasingly prevalent. However, even well designed, constrained-random verification methodologies can be ultimately ineffective (or even worse, misleading) if verification metrics related to native low power simulation are not identified, planned for, managed and tracked.

Low power coverage adds a new set of objectives to traditional coverage-driven verification methodologies:

  • Are all the design low power states defined and mapped in the UPF?
  • Have we completely exercised all of the required power states from the UPF?
  • Do we see illegal states/transitions?

Once all of the coverage metrics related to these objectives are defined, they must be tracked in the same coverage database as all other coverage metrics.

Native low power simulation is the inherent capability of today’s advanced simulation environments, such as VCS NLP, to accurately and comprehensively understand the structure and behavior of low power design intent, at RTL and at gate level for any stage of the implementation and verification flow. Clearly, native low power simulation at RTL requires a deep understanding of and experience in accommodating customer- and semiconductor vendor requirements in order to accurately infer low power models and circuits from IEEE1801 (UPF) low power design intent. In addition, effective native low power simulation also requires true voltage-level awareness to correctly simulate all low power modes and behaviors and accurately corrupt outputs, and as we discussed in my last blog post, integrated X-propagation semantics.

Native low power simulation can be as complex (and in some cases much more so!) as always-on simulation. It is imperative that relevant coverage metrics based on the analysis of input low power design intent—via reading UPF—be created and used intrinsically as part of the coverage-driven verification methodology. This verification effort should not be a separate process or activity; rather, to keep the effectiveness and efficiency benefits that coverage-driven verification brings, the coverage collection, review and debug for low power coverage metrics must be done in the same fashion and flow as any other user-defined coverage metrics, and they must reside natively in the same databases and tools flows as other metrics.

VCS’ coverage flows include automatic integrated coverage for low power objects defined or inferred from UPF low power design intent, and except for the blue boxes below, identical to traditional VCS coverage flows.


Figure 1. VCS Low Power Coverage Flow

VCS low power coverage metrics are defined as SystemVerilog covergroups, and are managed identically to all other covergroups. Low-power covergroups are automatically generated for PST, port supply, power switch and supply set states and transitions via a simple VCS compile switch. In addition, users may create their own custom low-power covergroups. Legal and illegal low power state transitions and sequences are specified in the UPF using describe_state_transition commands.

Coverage results may be easily viewed and analyzed in both the DVE GUI and via Synopsys’ Unified Report Generator (URG) text reports, providing various ways to visualize achievement towards low power coverage goals, and enabling efficient convergence in low power coverage flows.

Figure 2. Viewing Low Power Coverage Results in DVE GUI

Figure 3. Low Power Coverage Reports from URG

Flexible and efficient debug is also critical, so rapid cross probing with source UPF is also supported in DVE. Coverage results are available per test and per regression.

Figure 4. Low Power Coverage Analysis and Debug in DVE

VCS native low-power simulation fully supports low power verification objectives in coverage-driven verification methodologies. Critically, this support is not an add-on extension to standard flows and methodologies, but is built seamlessly into the overall VCS environment. Verification engineers can use VCS to automatically generate low power coverage metrics, and create user-defined custom metrics. By incorporating these new coverage metrics fully into their VCS verification planning, execution, management and debug flows, users can enable complete coverage-driven verification methodologies for the most advanced low power SoCs.

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