Special Report
How To Build Resilience Into Chips
Heterogeneous designs, customization, and increasing complexity open doors for hardware errors.
Taming Corner Explosion In Complex Chips
The number and severity of design corners is pushing the bounds of analysis, but new approaches are emerging.
Top Stories
Leveraging Data To Improve Productivity
Collecting, analyzing, and utilizing data can pay big benefits for design productivity, reliability, and yield.
Dealing With Performance Bottlenecks In SoCs
SoCs keep adding processing cores, but they are less likely to be fully utilized because the real bottlenecks are not being addressed.
News
Keysight Acquires Cliosoft
Deal boosts EDA portfolio with data management and IP asset tracking.
Blogs
Technology Editor Brian Bailey takes a quick dive into ChatGPT and concludes that while it is surprisingly good, it will not replace us anytime soon, in Will AI Take My Job?
Keysight’s Ben Miller predicts high-speed data center networks will play a crucial role in the emerging technologies of tomorrow, in The Vital Role Of 1.6T Networking In Emerging Technology.
Cadence’s Paul McLellan looks at what’s needed to establish a chiplet marketplace, from intellectual property concerns to interoperability, in How To Make Chiplets A Viable Market.
Synopsys’ James Chuang finds that integrating logic synthesis, place-and-route, and timing sign-off into a single step eliminates surprises in the implementation flow, in Beyond Human Reach: Meeting Design Targets Faster With AI-Driven Optimization.
Siemens EDA’s Kesmat Shahin explains why performing efficient early-stage LVS runs will simplify debugging, in Fast, Focused Early-Stage Circuit Verification Can Get You To Signoff Faster.
Codasip’s David Marsden highlights ready-to-use security that can be optimized for unique applications, in Make The Right Choices For Enhanced Security On RISC-V.
Renesas’ Toshio Kimura looks at a new way to measure the power consumed by home appliances and industrial equipment, in Smart Energy Metering For A Greener Future.
Sponsor White Papers
Achieve Dramatic Productivity And Turnaround Time Improvements In Early Design Electrical Rule Checking
How to speed up debug in early-stage design verification iterations and accelerate tape-out schedules.
Smart Devices Enabled To Efficiently Communicate, Sense, Hear, Act And Interact With User
Design trends on smart devices that are improving processing speed and power efficiency.
Advanced Modulation And Coding Challenges
Two modulation technologies that enable 400GE, each with its own set of challenges.
Efficient Verification Of RISC-V Processors
Applying a Swiss cheese model strategy.
Best Practices For Cybersecurity-Aware SoC Development With ISO 21434
How ISO/SAE 21434 compares to ISO 26262, and what the cybersecurity processes and best practices for product development are based on requirements of ISO/SAE 21434.
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