Top Stories
2.5D Integration: Big Chip Or Small PCB?
The industry is divided about the right materials, methodologies, and tools for interconnecting chiplets, and that can cause problems.
Chiplet IP Standards Are Just The Beginning
Data and protocol interoperability standards are needed for EDA tools, and there are more hurdles ahead. Customized chiplets will be required for AI applications.
Commercial Chiplet Ecosystem May Be A Decade Away
Technology and business hurdles must be addressed before widespread adoption.
Accellera Preps New Standard For Clock-Domain Crossing
Goal is to streamline the CDC flow between IP vendors, integrators, and tool vendors.
Latency, Interconnects, And Poker
Where this year’s Phil Kaufman Award winner placed his bets, and how he won.
Thinking Big: From Chips To Systems
Multi-die systems require new tools, technologies, and some very different approaches to design automation.
Videos
Integration Challenges For RISC-V Designs
Modifying the source code allows for democratization of design, but it adds some hurdles for design teams.
Blogs
Technology Editor Brian Bailey contends that with the disappearance of the ITRS roadmap, the industry lacks a unified voice to identify future EDA needs for timely implementation, in Design Tool Think Tank Required.
Movellus’ Barry Pangrle summarizes IC industry predictions that generative AI could enable more productivity and better designs, in Brain-Inspired, Silicon Optimized.
Keysight’s Emily Yan looks at how wide-bandgap semiconductors could redefine design and simulation workflows for the next decade, in What’s Next For Power Electronics? Beyond Silicon.
Arteris’ Frank Schirrmeister shows that significant effort is involved in developing coherent NoCs from scratch, in NoC Development – Make Or Buy?
Dana Neustadter (Synopsys), Ruud Derwig (Synopsys), and Martin Rösner (G+D) point to the deployment of an integrated SIM as a tamper-resistant secure element in a baseband SoC, in Navigating IoT Security.
Cadence’s Anika Sunda underscores how verification plan quality significantly influences project outcomes, in Weak Verification Plans Lead To Project Disarray.
Siemens EDA’s Terry Meeks digs into how earlier design-stage error detection and correction improves the efficiency of the IP design process, in Maximizing Efficiency And Productivity: The Benefits Of Shift Left Verification For IP Designers.
Sponsor White Papers
A Game-Changer For IP Designers: Design-Stage Verification
Shifting physical verification left in the flow makes it easier to locate and correct design errors earlier.
Understanding The Differences Between Oscilloscopes And Digitizers For Wideband Signal Acquisitions
The advantages and disadvantages of using oscilloscopes or wideband digitizers for wideband signal applications.
3D Connection Artifacts In PDN Measurements
A method for using simulation results to post-process measurements to remove coupling inherent in a launch structure from the two-port probe measurement methodology.
Remote Droop Detection And Response Use Case
System architects can mitigate droops with integrated droop response systems, which adapt dynamically to voltage droops (IR drops).
Advanced Design Planning In IC Compiler II
The datamodel and rethinking of the entire library and design paradigm reduces memory, provides massively improved throughput, and reduced turnaround times.
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