Top Stories
EDA Makes A Frenzied Push Into Machine Learning
All major vendors now incorporate ML in at least some of their tools, with more ambitious goals for AI in the future.
True 3D-IC Problems
Stacking logic requires solving some hidden issues; concerns about thermal dissipation may be the least of them.
AI Adoption Slow For Design Tools
While ML adoption is robust, full AI is slow to catch fire. But that could change in the future.
Designing For In-Circuit Monitors
Data from sensors is being used to address a wide variety of issues that can crop up at any point in a chip’s lifetime.
RISC-V Driving New Verification Concepts
Doing what has been done in the past only gets you so far, but RISC-V is causing some aspects of verification to be fundamentally rethought.
EDA Posts Q4 2022 Revenue Of $3.9B
All tool categories and regions show growth in 4Q22.
Blogs
Technology Editor Brian Bailey asks if reuse, which is now a staple for the semiconductor design industry, is ready to use RTL generated by AI, in Can AI Write RTL?
Synopsys’ Samad Parekh and Noman Hai look at design tradeoffs in the choice of multiplexer architecture, equalizer design, serialization technique, and output driver, in Design Challenges Of High-Speed Wireline Transmitters.
Expedera’s Paul Karazuba warns that although CIM can speed up multiplication operations, it comes with added risk and complexity, in Can Compute-In-Memory Bring New Benefits To Artificial Intelligence Inference?
Movellus’ Barry Pangrle looks at what’s in the roadmap for ramping new processes and packaging, in “TSMC Targets N2 Production For 2025.”
National Instruments’ Chen Chang and Alejandro Escobar Calderon explain why carriers are turning their focus to 5G mmWave alternatives, in What’s Next In Wireless Standard Adoption?
Keysight’s Jenn Mullen calls for automotive testing methods that keep up with the rapid iterations inherent in the software space, in The Drive To Disrupt: How Digital Twins Are Fueling Automotive Innovation.
Codasip’s Tora Fridholm recounts the building of a chip for event-based vision, inspired by the detection of light in the eyes and the processing of visual information in the brain, in Working With The NimbleAI Project To Push The Boundaries Of Neuromorphic Vision.
Siemens EDA’s Hossam Sarhan and Alexandre Arriordaz spell out why waiting until signoff to verify reliability compliance is no longer a practical or realistic option, in Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout.
Renesas’ Eldar Sido presents the benefits of a micro-architecture extension to replace lower to mid-tier DSP cores with on-chip processing, in Improved DSP And AI Performance On An MCU Core.
Cadence’s Paul McLellan points to keynotes that highlighted AI and data center communications, in Notes From CadenceLIVE Silicon Valley 2023.
Sponsor White Papers
Pre-Layout, Post-Layout Circuit Reliability
Do it early, do it often.
Impacts Of Process Flow, Scaling, And Variability On Interconnect Performance
Evaluating the performance of interconnects across three process flows — single damascene, dual damascene, and semi-damascene.
Meeting The Major Challenges Of Modern Memory Design
Three challenges stand out — scaling performance and capacity; ensuring silicon safety and reliability; and reducing development turnaround time.
Automated HW/SW Co-Design Of DSP Systems Composed Of Processors And Hardware Accelerators
As the number of smart data-acquisition devices grows, so does the amount of data requiring digital signal processing—compression, encryption, signal conditioning, and more.
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