Easy-To-Use Reliability Checks Throughout The Design Cycle From IP To Full-Chip Tapeout

Waiting until signoff to verify reliability compliance is no longer a practical or realistic option.


By Hossam Sarhan and Alexandre Arriordaz

With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff verification is no longer practical for design teams. There is a constant push to shift targeted verification activities “left” to earlier stages in the design flow. Finding and eliminating selected errors earlier during design and implementation, when they are typically much easier to fix, is now crucial to achieving tapeouts on schedule.

For example, many foundries now provide reliability rule decks to verify layouts are adequately protected against electrostatic discharge (ESD) and latch-up (LUP) events [1,2]. These foundry rule decks [3-8] validate that a circuit is electrically robust and compliant against foundry guidelines for these types of undesirable electrical events. However, given today’s tight design schedules, waiting until signoff to verify reliability compliance is no longer a practical or realistic option. Designers need to apply reliability verification checks throughout the design flow, from intellectual property (IP) to full-chip level, to find and fix reliability issues in earlier design stages and ensure they meet design schedules.

Multiple checks are needed to ensure reliability of a design, starting with reliability topological checks such as design verification of device types, continuing to cross-power-domain verification, through to layout reliability verification such as checking the symmetry of sensitive analog devices, and ending with full-chip layout verification such as ESD checks. Because most designers are not reliability experts, they may not be confident in their selection and configuration of the appropriate reliability checks in early design stages. Providing an easy-to-use solution that supplements foundry reliability flows throughout the design cycle can help provide that confidence and ensure fast, accurate early-stage reliability verification.

User-friendly design-stage reliability verification

During a design and verification cycle, designers run checks, review the results, update their design to fix errors or optimize configurations, then re-run the checks again to confirm the changes were correct and no additional errors were introduced. For example, in analog layout designs, designers must observe the common best practice for a group of devices, such as symmetry or common centroid compliance [9]. To do that in early design stages, designers select a group of devices (e.g., a differential pair), run a check to verify the symmetry only on these devices, review and confirm the results, then integrate that group of devices to the full cell and run the interconnect checks.

A solution that enables all designers to perform this design-stage reliability verification quickly and accurately is needed. The Calibre PERC reliability platform packaged checks flow provides pre-coded reliability checks in a user-friendly framework that permits simple selection and configuration of these checks from within implementation tools, maximizing ease-of-use and minimizing runtime setup [10].

By leveraging the Calibre PERC packaged check framework, designers can quickly and easily combine multiple pre-coded reliability checks into a single run for reliability verification of a design. Designers can select these pre-coded checks through interactive check selection and configuration (figure 1).

Fig. 1: Flow chart showing design cycle iterations using Calibre PERC packaged checks.

Reliability coverage and the nature of the specific checks available to designers for a given run are dependent on the checks contained within the particular check library being referenced. A check library may contain the complete set of reliability checks available, or a subset focused only on specific design requirements. Specialized check libraries typically contain only those checks categorized by their intended use:

  • Design verification checks include in-design-focused checks like device count, level shifter, circuit pattern identification, electrical overstress (EOS) checks, and multiple power domain checks [11].
  • Layout reliability checks address logic-driven layout checks used to enhance layout reliability, such as LUP, crosstalk, or voltage-aware design rule checking (VA-DRC) checks [12].
  • ESDA checks enable designers to apply packaged checks aligned with ESD Association (ESDA) recommendations [13-15]. ESD topology, point-to-point (P2P) and current density (CD) checks (device- or cell-based), cross-power-domain checks, and IO ring checks provide a solid foundation on which design companies can build their individualized reliability verification methodology.
  • Analog layout checks focus on improving reliability for designs with extreme reliability needs, such as automotive or memory designs [16]. For these layouts, symmetry, common centroid, and matched orientation verification are crucial, and compliance must be verified with more than visual inspection, given their circuit complexity.

Interactive check selection and configuration

Ensuring accurate check command line configuration and invocation can be time-consuming and error-prone. The Calibre PERC packaged checks graphical user interface (GUI) provides designers of all experience levels with a complete and user-friendly process for selecting, configuring, and running Calibre PERC packaged checks.

The Calibre PERC packaged checks GUI provides a powerful, user-friendly interface that enables designers to quickly and accurately select and configure checks from a check library (figure 2). A check library can be configured to show only those checks relevant to a specific design team—for example, an analog design team may only need to see analog layout-related checks, while an ESD design team would want to see ESD-related checks (ESD topology and P2P/CD checks). Designers can use the Calibre PERC GUI to quickly navigate through the check libraries, select the desired checks, and easily configure the check parameters according to their design criteria.

Fig. 2: Calibre PERC packaged checks GUI showing an ESD checks selection.

The Calibre PERC packaged check GUI also provides a seamless integration with the Calibre Interactive invocation and Calibre RVE results viewer interfaces. This integration provides designers with a unified experience from selecting, configuring, and running reliability checks to reviewing results with cross-reference highlighting (figure 3).

Fig. 3: (a) Running level shifter detection check using Calibre Interactive invocation, and (b) validating results using Calibre RVE results viewer.


Given today’s tight design schedules, waiting until signoff to verify reliability compliance is no longer a practical or realistic option. To ensure design schedules can be met while maintaining design reliability, Calibre PERC packaged checks provide design teams with a powerful flow for early design-stage reliability verification. To further facilitate these early reliability verification cycles, a customizable, user-friendly packaged checks GUI enables designers to browse check libraries, easily select and configure the needed checks based on their design criteria, and run the checks using the Calibre PERC platform. Designers can then analyze the results using the Calibre RVE results viewer, fix any design issues, and relaunch the check(s) in an interactive flow. Together the Calibre PERC packaged checks flow and GUI enable designers to quickly and easily cover a wide range of critical packaged reliability checks earlier in the design flow. This combination enables design companies to implement their shift-left strategies and improve productivity while leveraging proven Calibre PERC reliability verification throughout the design flow to address their design reliability challenges with ease and Calibre confidence.

Want to learn more about these pre-coded reliability checks, and see how you could be using the Calibre PERC packaged checks GUI to verify and optimize your designs more quickly? Our technical paper, Pre-layout/post-layout circuit reliability verification…Do it early, do it often, provides a more in-depth discussion.

Alexandre Arriordaz is a senior product engineering manager for Calibre Design Solutions at Siemens Digital Industries Software, focusing primarily on the Calibre PERC reliability platform. He also serves as a project interface for various European projects investigating R&D topics such as 3D-IC or silicon photonics. Prior to joining Siemens, Arriordaz was a full-custom design engineer, working on advanced testchip/SRAM compiler developments. He holds a master’s degree in electronics from the University de Nice-Sophia-Antipolis, France.


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