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A Reliable I/O Ring For A Reliable SoC

Integrate disparate I/O ring rules from various IPs to create a design with robust reliability.

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What is an input/output (I/O) ring, and why should I care about it? If you’re a system-on-chip (SoC) designer, you had better know the answer to that question. SoCs are the darlings of the semiconductor industry—they combine all the typical functionality of a computer (central processing unit (CPU), memory, input/output (I/O) ports, and storage) on a single chip. They’re particularly popular with the mobile electronics crowd, because they require a lot less power and are much smaller than multi-chip designs. For example, you can put SoCs inside tiny little drones and fly them in synchronized patterns to create light shows (Figure 1).


Figure 1. 2018 Winter Olympics drone light show. (source: Intel Corporation)

The opposite side of all this capability is how reliably and consistently the SoC performs. With increasingly complex products performing much more critical tasks than lighting up the night sky, ensuring the SoC design is protected from reliability issues such as such as electrostatic discharge (ESD), latch-up, electromigration (EM), and IR drop is essential. That’s where the I/O ring comes in.

All SoCs are divided into two functional areas: the core and the I/O controls. The core performs the logic for which the chip is designed. If, for example, any incoming signal has a voltage level higher than the core level and that signal reaches the core, a core failure may occur. To prevent that from happening, SoC designers combine multiple protection structures to form an I/O ring around the core (Figure 2).


Figure 2. SoC I/O protection ring. (source: Mentor, a Siemens Business)

During design and verification, SoC designers must ensure that the I/O ring is properly constructed and provides the necessary protection. Here’s what makes that a unique challenge—SoCs typically contain multiple intellectual property (IP) blocks provided by different specialized IP providers. Each IP block comes with its own I/O ring, as well as rules for the cell placement within that I/O ring. I/O placement rules are based on the IP design architecture combined with the IP provider’s expertise and experience, and typically vary significantly from one IP provider to another.

When all those IPs are combined into a SoC layout, the SoC designer must create an SoC I/O ring that not only provides the necessary reliability protection across the entire SoC, but also integrates all of the disparate I/O ring rules for the IPs. If there is a conflict, the SoC designer must work with the IP provider(s) to find a solution.

Designing and verifying I/O rings on today’s complex SoCs requires a variety of sequential stages, all of which are equally essential to successful completion. In the past, SoC designers had little choice but to perform this reliability checking manually. Not only is this a time-consuming process, and prone to human error, but it was typically performed late in the design flow, after all the IP blocks had been incorporated. That meant any errors that were found were extremely difficult to correct, and correcting one often created another, which ended up delaying tapeout schedules as designers laboriously worked through the debugging process.

At today’s advanced nodes, with the increasing complexity of designs, reliability verification has become even more challenging. In many designs, physical requirements may now vary depending on the electrical specifications, and vice-versa. Implementing context-aware checks that can validate the accurate combination requires knowledge of both the physical and electrical conditions in a layout.

With the introduction of new verification capabilities, options for automated I/O ring verification are now practical. Electronic design automation (EDA) reliability checking tools, such as the Calibre PERC reliability platform from Mentor, a Siemens business, can automatically correlate both netlist and layout information in a single check, enabling designers to quickly and accurately analyze layout restrictions that are defined by connectivity constraints. Incorporating these checks into an automated LEF/DEF I/O ring checker framework also allows designers to verify SoC compliance with a wide variety of foundry and IP ESD placement rules in LEF/DEF designs, when there is still time to optimize and refine the design before beginning final signoff verification (Figure 3).


Figure 3. I/O ring check flow. (source: Mentor, a Siemens Business)

In place of extensive textual guidelines, IP providers can use the I/O ring checker framework to provide their I/O placement rules and define all their IP placement constraints in an XML-based input constraint file, even without any knowledge of Calibre PERC rule coding (Figure 4). These constraint files are supplied with the IP, and can be quickly assimilated into the SoC I/O ring check ruleset for use with Calibre PERC verification.


Figure 4. Individual IP rules can be easily integrated into the SoC constraints file. (source: Mentor, a Siemens Business)

Even with this type of checking capability, I/O ring reliability checks can be difficult to understand and apply correctly, especially for the broad non-specialized group of designers who do not deal with reliability verification day in and day out. Providing these users simple-to-use access to the powerful reliability verification capabilities of possible checks is paramount for successful adoption.

To ensure that all SoC designers, no matter their level of experience and expertise, could accurately invoke reliability verification on their I/O ring configurations, the Calibre PERC reliability platform also introduced the I/O ring check package—a set of five configurable and flexible generic top-level pad checks that allows the SoC designer more flexibility to configure specific I/O placement rules for count, ratio, spacing, pitch, and abutment for any type of cell (Table 1). By customizing these five checks with user-written constraints, not only can designers implement all legacy ESD rule checks, but also any latch-up constraints, power management requirements, and other reliability conditions that can be defined by placement rules.


Table 1. I/O ring check package

To apply a given rule to an isolated section of the I/O ring, SoC designers define the “isolated section” in the constraint file, using cell names or nets names. By defining each isolated section, designers can apply different variations of the five checks to different sections of the I/O ring. The Calibre PERC reliability platform automatically detects these defined isolated sections of the I/O ring (I/O domains), using either isolated cell type information or net connectivity, and applies the appropriate check to that section. For example, if two different power domains have two different rule sets, the Calibre PERC reliability platform automatically detects each power domain (isolated section) based on the power ground nets and metal layer used for power ground routing.

Designers also have the option of creating a debug hint that provides a plain text description of the constraint to help during error debugging. This can be extremely helpful when reliability verification is being performed by a team, who may not all have the same level of knowledge and experience.

SoC I/O ring protection is essential to the accurate and reliable operation of SoCs. Ensuring that an SoC I/O ring is properly constructed to provide the necessary protection against reliability impacts is a critical part of the design flow. The introduction of innovative checking capabilities, combined with new interfaces that support standardized, customizable I/O ring checking, now enables SoC designers to confidently identify and correct I/O ring violations early in the design flow, when correction and optimization can be implemented more easily. Accurate, standardized, and repeatable reliability verification ensures that SoC I/O rings not only provide the needed protection, but comply with all IP and SoC design rules that protect them against operational failures. Because we all want more drone light shows (Figure 5). And reliable SoCs.


Figure 5. Intel 50th anniversary drone light show. (source: Intel Corporation)

For more information, download our whitepaper, “Enhancing I/O ring checks for consistent, customizable verification.”



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