Top Stories
Debugging Embedded Applications
Software and hardware interdependencies complicate debug in embedded designs. New approaches are maturing to help reduce debug time.
What’s Next For Emulation
Technologies must evolve to keep up with changing demands, and emulation is no exception.
Partitioning For Better Performance And Power
Design tradeoffs become more complex, shift to the system level.
High-Level Synthesis For RISC-V
Abstraction is the key to custom processor design and verification, but defining the right language and tool flow is a work in progress.
What’s Missing For Designing Chips At The System Level
Customization and multi-chip packages make it far more difficult to create chips using traditional approaches.
Blogs
Technology Editor Brian Bailey argues that while no tool lasts forever, sometimes you get blindsided by the changes you can’t anticipate, in Dealing With Market Shifts.
Cadence’s Frank Schirrmeister stresses that planning and analyzing fault campaigns holistically are key in safety design, in Functional Safety Across Analog And Digital Domains.
Siemens EDA’s Neil Hand says the cost of complexity calls for a change in the way we think of verification, in Debug Solutions For Designers Accelerate Time To Verification.
Synopsys’ Anika Malhotra looks at using AI techniques to determine which constrained random tests are most effective for improving coverage, in Intelligent Coverage Optimization: Verification Closure In Hyperdrive.
Codasip’s Roddy Urquhart shows a way to add custom instructions to a processor without error-prone manual editing, in Customize Off-The-Shelf Processor IP.
The Road To Osmosis
Sharing information and pushing the boundaries of formal verification.
White Papers
Microchip Sees Significant Productivity Gains In Mature-Node Custom IC Design With In-Design Signoff DRC.
Co-Packaged Optics And The Evolution Of Switch/Optical Interconnects In Data Centers.
Hierarchical Verification For EC-FPGA Flow.
3D-IC Design Challenges And Requirements.
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