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3D-IC Design Challenges And Requirements

The capabilities needed for cost-effective 3D-IC design.

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As demands accelerate for increasing density, higher bandwidths, and lower power, many IC design and packaging teams are taking a close look at vertical stacking multiple chips and chiplets. This technology, called 3D-IC, promises many advantages over traditional single-die planar designs. Some are using the term “More-than-Moore” to describe the potential of this new technology. Integration by stacking die and using advanced packaging technologies allows designers to cram more functionality into much smaller form factors, while improving performance and reducing costs. 3D-IC architectures can integrate multiple homogenous and heterogeneous die/chiplets, such as logic, memory, analog, and RF, into a single design. This provides an alternative to monolithic system-on-chip (SoC) integration, potentially bypassing the expensive move to a new process node for all of the functionality designers want to place in a single design. With comprehensive offerings in analog and digital implementation, packaging, and PCB design tools, Cadence is uniquely positioned to support the 3D-IC revolution and to provide the capabilities that are needed for cost effective design of 3D-ICs.

By John Park, Product Management Group Director, Cadence

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