Top Stories

Can Big Data Help Coverage Closure?
When does a large amount of data become Big Data, and could system-level verification benefit from it?

Applying Machine Learning To Chips
The goal is to improve quality while reducing time to revenue, but it’s not always so clear-cut.

Merging Verification With Validation
Are these really separate tasks, or just a limitation of tools and flows?

Videos

Tech Talk: Automotive Design
How to speed up time to market while improving quality in automotive chips.

Tech Talk: Faster Simulation
Why simulation is still so important and how to make it run faster.

Blogs

Editor In Chief Ed Sperling finds commonly used metrics are taking on new meaning as electronics begin playing a bigger role, in Smaller, Faster, Cheaper—But Different.

Technology Editor Brian Bailey examines the relationship of two critical elements in chip design, in Verification And Validation Brothers.

Mentor’s Stephen Pateras contends that new manufacturing and in-system test strategies are required to meet safety requirements, in How Automotive ICs Are Reshaping Semiconductor Test.

Synopsys’ Kenneth Chang explains why power integrity needs to be considered much earlier in the design flow, with In-Design Rail Analysis Is A Beautiful Thing.

eSilicon’s Mike Gianfagna warns that managing the massive amounts of data generated today won’t come cheap, in Deep Learning Market Forces.

Aldec’s Henry Chan shows how to use native SystemVerilog constructs as metrics for verification closure, in Simplifying SystemVerilog Functional Coverage.

Cadence’s Frank Schirrmeister looks at the intersection of key industry trends, in Embedded World 2018: Security, Safety, And Digital Twins.

OneSpin’s Sergio Marchese questions how many ways there are to solve a problem, in Asterix In The Land Of Soduku: The Fast, The Elegant, And The Popular Formal Solvers.