How Automotive ICs Are Reshaping Semiconductor Test

New manufacturing and in-system test strategies are required to meet safety requirements.


The growth of a new IC market creates ripples along the entire supply chain. Today, we see the semiconductor industry reacting to the needs of the growing automotive IC market, including the development of new IC test tools and methods.

The automotive IC market is far and away the fastest growing end-use market with 15% CAGR (according to IC Insights). It is also seeing many new players. Market leaders like NXP, Infineon, ST, Texas Instruments, On Semiconductor, and Bosch are now joined by Intel, Qualcomm, Apple, Marvell, Nvidia, and Samsung.

The demand goes far beyond electronics for established car features, like radio, automatic windows, and power steering. Today, the race is on to create ICs for safety-related and autonomous driving features. ICs for safety-critical car systems come with stringent new requirements as defined by ISO 26262, which includes guidelines for semiconductors in the upcoming version. There are also new processing demands as the computational load increases for situation-analysis functions. Automotive ICs are increasingly using leading-edge process nodes and the most advanced AI algorithms. Nvidia, for example, offers their Drive PX-2 self-driving platform, which was manufactured with 16nm FinFET and boasts 8 Teraflops of compute performance. The Mobileye EyeQ5, scheduled for 2020 release, could be developed on the 7nm process.

So, lots of semiconductor companies are designing very complex devices at the most advanced nodes that need to adhere to the ISO 26262 standard – it is something of a perfect storm from a semiconductor test perspective. The situation demands some changes in how we do manufacturing and in-system test to achieve functionally safe automotive electronics.

The test strategy for automotive ICs has two main areas of concern:

  1. Ensure manufactured devices are defect free – aiming for zero DPPM in a cost-effective way.
  2. Ensure ongoing, proper operation through the life of the device – find and fix new defects that arise during operation.

For manufacturing quality, the stakes are little different than in the past, when consumer products could tolerate a somewhat higher defect level. For safety-related devices, there is less wiggle room on defects.

Traditional manufacturing test involves high-level modeling defects that can occur in the IC, then pattern generation based on those models. It typically is good enough and cost-effective. With automotive, we need to be more specific and ensure that all possible defects are covered – a concept called defect-oriented test. For defect-oriented test, you generate the test patterns that will provide higher coverage by looking at the chip layout, the GDSII, and extracting all possible defect locations. Those are then modeled and patterns are generated as usual. The modeling is based on analog simulation, and is referred to as Cell-aware ATPG – electrical defects are mapped to cell-level transistor models. Cell-aware test is an extremely effective way to improve DDPM.

Another newer technique to reduce DDPM involves examining the interconnect between standard cells using critical area analysis to generate a complete set of critical area based fault models. With netlist-level models, applying critical-area analysis maximizes quality while keeping pattern count under control by finding the defects that have a higher probability of occurring based on the layout.

After the devices are manufactured and deployed in an automotive system, how do you ensure they continue to be defect free over time? Through runtime monitoring. The technology for runtime monitoring has advanced beyond simple built-in-self-test (BIST) circuitry. Today, we create a communication infrastructure between the ICs and the system-level software (safety processor) so that the car system has clear communication with the electronic systems, including the ICs in them. That infrastructure is IJTAG-based IEEE 1687. Every device has IJTAG architecture that allows monitoring of the device and reconfigurable access to CPUs, ROMs, and any on-chip test IP. An in-system test controller (such as Tessent MissionMode) manages the communication between the on-chip IP and external systems.

At the board level, the in-system test controllers are connected to a bus (vehicle bus) to communicate to the safety processor of the car, which can then run any of the test resources on the devices. There are several ways to configure the controller – real-time CPU access, or use stored sets of instructions—to balance between latency and chip area overhead.

So how do you perform test during operation? Logic BIST tests all logic on chip, captures the response into scan chains, and lets a signature register decide if the device is go/no-go. In automotive systems, a new constraint on logic BIST includes power usage. Specifically, you don’t want large spikes in power usage, so logic BIST is improving to use less power and offer a more even power signature.

Another challenge with logic BIST is that the random tests decrease in effectiveness as more tests are applied. If the time budget for runtime testing is restricted, as in automotive devices, you need to be able to test more in less time. Test points are a great technology for this end because they reduce the test time and catch defects that are resistant to random patterns. This means you need fewer random patterns to get to 90% defect coverage.

Other strategies to reduce test time include breaking tests into more sessions and supplementing the random patterns with compressed test data (ATPG patterns) through a hybrid ATPG/logic BIST architecture. In a hybrid ATPG/logic BIST setup, patterns are stored until retrieved by the MissionMode controller and applied through the scan chains on the device.

For runtime testing of memories, we use memory BIST, in which patterns are generated algorithmically. A key factor for automotive ICs is to test the memories periodically and repair them. However, memory test is a destructive process, meaning that historically you had to take the memory offline to test it, and the contents of the memory are destroyed. For automotive ICs, we use a newer method of non-destructive testing – the memory is tested for just a few clock cycles at a time and only two locations are tested at a time. Once those locations are tested, the original contents are replaced back into the memory. This method of memory BIST never interferes with the logic functioning.

The fast-growing automotive IC market is changing the way we think about semiconductor test. New technologies, tools, and methods help to enable the emergence of autonomous vehicles.

Leave a Reply