Top Stories
What Are EDA’s Big 3 Thinking?
Messages delivered by all three CEOs to their respective users point to trouble spots, opportunities and what’s ahead for EDA.
Graphing Toward Standardization
The industry seems unified when it comes to needing new technologies for system-level verification, but have we explored the possibilities enough before standardizing on one?
How To Improve Debug Productivity
Writing test benches is relatively quick, but up to 90% of total verification time is spent debugging. Here are some recommendations from the front lines to improve debug productivity.
Design Efficiency Metrics Growing Fuzzier
With the old measurements no longer useful, companies are struggling to come up with benchmarks that make sense.
Extending UVM To Analog
Analog/mixed-signal content in SoCs needs to be modeled in a similar way as the digital content but does UVM make sense for pure analog? Perhaps not.
Does Formal Have You Covered?
While most verification standards did not consider formal, they provide a wealth of data that can be mined. Questions still remain about when you have done enough verification.
Blogs
Editor in chief Ed Sperling says you can tell what’s real and what isn’t by the amount of money being invested in tools and equipment in Follow The Investments.
Technology Editor Brian Bailey attends a speech about the future of Ivy League schools and why that model no longer works in Ivy League Colleges Crumbling.
Cadence’s Frank Schirrmeister says that as design windows shrink, the so-called “shift-left” pressures are rising, in How To Shorten Hardware-Software Development Cycles.
Synopsys’ Tom De Schutter uses the gaming world as a model for new design possibilities in What Should I Build?
eSilicon’s Mike Gianfagna laments our fading ability to talk to each other in The Fading Art of Person-to-Person Communication.
And Arteris’ Kurt Shuler says the people define the conference, not the other way around, in SoC Assembly And IP Reuse.
