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There’s plenty of talk about 2.5D, 3D and fan outs, but there’s real investment in other places.

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Where is design heading over the next few years. The best way to tell that is to find out where the development dollars are going, and foundries and tools always precede actual designs.

The foundries are starting to spend money—lots of it—on finFETs and 28nm. And while they’re talking about 2.5D and 3D, the money isn’t going there just yet. In fact, there are two different processes for finFETs at GlobalFoundries and Samsung, one that was just announced last week—LPE—and a second enhanced version—LPP (yes, that is a completely counterintuitive acronym), which improves power and performance and which will be available by the end of this year.

Looking back a couple years ago, executives at GlobalFoundries, Samsung and TSMC all publicly said that they would move to finFETs, but no one wanted to be the first to jump into the market. Fast forward to today and they’re actually investing in tools—TSMC just certified a slew of tools for version 1.0 of the first finFET process—and they’re buying equipment to build chips at advanced nodes. This is no longer just talk. The mobile market needs to push forward for PPA reasons, and the time has come to make that happen.

Meanwhile, the foundries are prepping 28nm to become the mainstream node, based on the assumption that more companies will hang at that node for longer than anytime in the past. The wild card there is whether EUV finally shows up to replace 193nm immersion lithography and eliminates the need for double patterning at 20/16/14nm. Don’t hold your breath on that one. It was supposed to be ready at 65nm, and now it likely will miss 10nm. Moreover, 28nm has a lot of life in it because at least some of the power/performance benefits of finFETs can be achieved with different materials and processes.

Fan-outs—basically swallowing up more of the PCB into a package—also are beginning to happen, although ultimately they could use photonics as the communications vehicle between various components in that package. That approach inevitably will lead to more utilization of interposers, but volume production is needed to make 2.5D really take off, and the sticking point there is the cost of the interposer. It will take time to fit all the pieces together, but it will have to happen simply because the interconnects at 10nm are looking very ugly. As a point of comparison, 16/14nm has been in the works for a half-dozen years, and the process technology is just now hitting version 1.0.

There are even doubts about what comes next for full 3D stacking. TSVs are a definite breakthrough in performance and power, but they create stress on thin die and subsequent thermal issues when they are implanted into the die. So far, that hasn’t been resolved, which is why there is work underway to use a 128-bit bus on the outside of the chip package rather than through the middle. This is basically a flip-chip interconnect to a memory mounted on an SoC, and sources say the approach is showing some positive results.

The best judge of what’s real and what isn’t, though, is where and when the foundries spend money on equipment. They’re holding back as long as they can these days on placing bets because those investments are huge—tens of billions of dollars in some cases. But when they do start spending, you can expect everything to ramp quickly. The question is what’s next, and if you talk to two people within any same foundry you’re likely to get two different answers. Design teams aren’t the only ones who are confused.

The work under way at universities on carbon nanotubes, gate-all-around FETs, biological transistors and memory and spintronics could have major implications for the future of semiconductors, as well. But it will be the outflow of big sums of money that will be the real indication of where the industry will go next, and so far that money is heading into the usual places.