Special Report
Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
But the inability to utilize leading-edge process nodes has created opportunities for small and midsize chip developers in multi-die design, along with some sophisticated architectural design tradeoffs.
Top Stories
Creating Agentic EDA Methodologies
Current approaches involve multiple tools, vendors, designs, data formats, and abstractions. Can agents really use them all?
NoC Coherency Challenges Balloon With AI SoCs And Chiplets
Complex chips need coherent and non-coherent sub-NoCs to ensure efficient data paths. Correct hierarchy is essential.
AI’s Potential And Limitations In Chip Design
Full automation is still a goal, but humans will still be in the loop for the foreseeable future.
AI Growing Impact On Chip Design And EDA Tools
Demand for faster design and more automation grows from key customers.
Designing Chips In The Context Of Rapidly Evolving AI
Long‑running agents, tool-calling LLMs, and multimodal chaos are rewriting edge compute rules, and making chip design more challenging.
Video
Why Proof Convergence Matters
Leveraging patterns in formal verification to reach sign-off faster.
Opinion
Hardware From Specifications Using AI
Can AI really generate hardware from specifications? It may not matter, because that’s only a small part of the problem.
Sponsor Blogs
Vinci’s Satish Radhakrishnan looks at the challenges of isolated checkpoints for semiconductor design simulation, in From Simulation Checkpoints To Continuous Physics.
Siemens EDA’s James Paris explains how to turn billions of violations into actionable insights, in Transforming DRC Closure At Advanced Nodes.
Cadence’s Priyadarshini N D examines the impact of integrating advanced equalization algorithms into channel simulations on eye diagrams, BER, and timing margins, in Unlocking High-Speed Serial Link Signal Integrity With AMI Model.
Arteris’ Andy Nightingale shows why the boundaries between IP reuse, interconnect design, and hardware-software integration are no longer independent, in Facilitating Complex SoC Design Through Automation And Integration.
Keysight EDA’s Maria Castillo points to design gaps in advanced package designs and what to do about them, in How To Streamline Your Advanced Package Interconnect Designs.
Synopsys’ Manoz Palaparthi finds traditional simulations lack an understanding of clocking requirements and cannot handle the complete clock network of a large chip, in Solving Clock Signal Integrity And Jitter Issues.
Baya Systems’ Nandan Nayampally discusses the importance of scalable AMBA-compliant system connectivity, in From Standards to Systems: The Chiplet Era On Arm.
Sponsor White Papers
Assuring Comprehensive Security Coverage In Hardware Design
Security coverage is a key component of a systematic framework for comprehensive, traceable security verification.
From Silos To Systems, From Data To Insight
Transform fragmented, siloed data into a governed, connected, and reusable organizational knowledge base.
Building An AI Chip: Silicon Design And Advanced Packaging
The second key stage of AI chip design: silicon design and packaging.
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