Special Report
Multiple Challenges Emerge With Physical AI System Design
Workloads, system performance, and the need to continually learn and adapt are demolishing constraints that have made chip design and verification consistent and reliable.
Top Stories
Thermal, Mechanical, And Material Stresses Grow With Die Stacking
More analysis and more data are needed to predict how different dies will interact in the same package.
Even With AI Inroads, Human Chip Designers Still Essential
Engineers are still needed at key points throughout the design pipeline.
Advances In Formal Verification Technology
It’s the only way to prove that a design is correct. Recent advances continue to make it better.
How To Cool 3D-ICs
Tool chains need improvement as chipmakers begin stacking AI chips, increasing the thermal density and unpredictability over time.
How 3D-IC Will Change Chip Design
Stacking dies will dramatically improve performance, but it’s still a work in progress.
Video
Multi-Die Verification
How to keep everything synchronized in a chiplet-based design.
Opinion
The Next Big Thing
When looking forward in EDA, disruption is always seen as the way to make big gains. But when you look back, large gains often come from a lot of small changes.
Sponsor Blogs
Siemens EDA’s Reetika describes a flexible approach for RDC verification that allows skip-depth to be defined on a per-path basis, in Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops.
Synopsys’ Suresh Babu Barla and Rimpy Chugh explain why it’s important to fix as many design issues as possible in RTL while ensuring the implementation flow does not introduce new problems, in Top Five Trends In RTL Signoff.
Arteris’ Andy Nightingale contends that performance is no longer just about achieving more speed at any cost, in Efficiency Defines The Future Of Data Movement.
Cadence’s Felipe Gonçalves shows the benefits of retransmitting only relevant data to optimize link efficiency, in Enhancing PCIe 6.0 Performance: Flit Sequence Numbers And Selective NAK Explained.
Sponsor White Papers
Ebook: The Impact of AI On Data Center Design
How AI is not just a power-consumptive curse but also a boon, because it can be used to ensure continually smooth data center operations.
Developing RISC-V Compute Subsystems
The combination of high-performance RISC-V CPU IP and advanced interconnect technology offers high performance, power efficiency, flexibility, and scalability.
Smart Handling Of Reset Domain Crossings To Non-Resettable Flip-Flops
How to distinguish between safe and unsafe RDCs.
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