Top Five Trends In RTL Signoff

By Suresh Babu Barla and Rimpy Chugh

The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-related issues necessitate modifications at the register transfer level (RTL). These changes trigger a complete re-analysis of the design, requiring the team to repeat the entire design flow—from verification and analysis to implementation. Each cycle of code revision, execution, and result validation consumes valuable time and resources, making late-stage corrections both inefficient and costly.

The only solution is to shift even further left, so that as many signoff steps as possible are completed at the RTL stage. The concept of RTL signoff is not new, but its practical application is evolving rapidly and improving all the time. The goal is to fix as many design issues as possible in the RTL code, while ensuring that the implementation flow does not introduce new problems. This post summarizes five current trends in RTL signoff that are making the process even faster and better.

Trend 1: Improving design quality with advanced lint

Traditionally, the focus for design correctness was on functional verification with simulation and formal methods. These remain major parts of the effort at the RTL stage but are supplemented by a wide range of lint checks. Many basic coding errors that would cause simulation or synthesis to fail can be caught much earlier by lint checking the RTL code.  Rule violations can be debugged quickly at the source, reducing both functional verification and implementation time.

Today’s advanced lint solutions go far beyond simple syntactic and semantic checks. Checks cover design connectivity, power, scan readiness, identifying abort points causing longer runtimes during logical equivalence checking (LEC), and more. Debugging the errors found is much easier with the use of AI and machine learning (ML) to perform root cause analysis (RCA). Reduction in “noisy” checking, hierarchical lint, smart rule waivers, and advanced lint management all make it possible to analyze and improve the quality of very large RTL designs.

Trend 2: Avoiding silicon bug escapes with advanced clock and glitch checks

In addition to coding errors, finding clock domain crossing (CDC) errors is critical; if they escape to silicon, they are likely to require a chip respin to fix. Gaining confidence in the functional correctness of the CDC constraints and protocols during structural CDC analysis is also important to avoid bug escapes. Such functional correctness using an integration of structural, formal and simulation techniques is a must for getting 100% confidence on zero functional CDC bugs.

Other types of critical functional glitch errors can now also be detected at the RTL stage. Checks ensure that multiplexers on clock trees, multicycle paths (MCPs), and false paths (FPs) are glitch-free. Such issues cannot be detected by static timing analysis (STA) or standalone simulation technologies. Finding and fixing these problems early in the project timeline helps avoids glitch bug escapes to later project stages or silicon, minimizes loops through implementation, and avoids a costly respin.

Trend 3: Correct-by-construction netlists with automated CDC signoff

Finding and fixing CDC issues at the RTL stage is clearly beneficial, but a lot of the value can be reversed if errors resurface or new errors are introduced during the synthesis process. This mandates that designers re-review CDC violations at the netlist level, which duplicates the effort made at the RTL stage. Reviewing the netlist CDC violations from scratch compromises the savings provided by the initial shift left. Converging so that most of the netlist violations match the RTL results may require many iterations. Maximizing mapping of netlist violations, constraints, and waivers with RTL violations, constraints, and waivers in an automated manner is a must for designer review to be achievable in a realistic timeframe. Reusing RTL constraints and waivers at the netlist level greatly reduces the amount of CDC review.

With such an automated out-of-the-box RTL-to-Netlist Mapping, designers get to do faster review in a reasonable timeframe. However, this still forces them to do error-prone engineering change order (ECO) fixes (hand-coding of gates at the netlist level) for resolving these resurfaced CDC violations. The better approach is to have a post-synthesis netlist that is correct by construction in terms of CDC behavior for asynchronous paths that existed at RTL and is pre-verified.

A CDC-aware implementation flow avoids this whole issue by ensuring that CDC paths validated at the RTL stage remain intact during synthesis. This prevents CDC errors from resurfacing on the asynchronous paths already validated at the RTL stage while also ensuring that designers do not need to make manual ECO fixes for these CDC paths. Such a flow also avoids most new CDC issues or glitches due to logic transformation during synthesis or manual changes. The combination of CDC-aware implementation followed by automated netlist CDC signoff ensures that the designer has to fix only a small number of new CDC violations at netlist that didn’t exist at RTL. This makes netlist CDC closure possible with 100% signoff confidence.

Trend 4: Cleaner design with scenario-based and cycle-aware RDC checks

Similar to CDCs, reset domain crossings (RDCs) are a risk for design errors that could require a respin if they can’t be fixed with software. RDC checks are available as part of the signoff process, but these are not as simple as they might seem. The complexity and size of designs lead to an unmanageable signoff review cycle, especially since RDC checks tend to be noisy in reporting potential issues that are not actually design errors. The scope of RDC analysis must cover all flip-flops in the design, whether or not they have reset pins. RDC checks can also be noisy if the reset architecture setup is not defined properly based on design functionality.

Modern RTL signoff solutions use scenario-based and cycle-aware RDC to reduce noise, enable faster and more accurate analysis, and accelerate RDC signoff. The scenarios for different types of resets can be diverse and complex, so the ability to capture these leads to cleaner results. A scenario-based approach helps to mimic the design functionality and find unexpected RDC corruption issues, along with checking functional correctness. Cycle-aware RDC factors in clock-cycle delays in data paths to gain better quality of results. Cycle-aware analysis enables checking that corruption is blocked at the destination by making sure that resets reach the destination before corruption does. Together, these two techniques enable robust RDC checks even on the largest chip designs.

Trend 5: Easier debug of optimized registers with root cause grouping

As synthesis tools have become more sophisticated, they have performed greater transformation of designs from RTL to netlist. One example is unintentional optimization of register blocks per design intent, which can result in late-stage surprises when designers try to find root causes for registers optimized during synthesis. Manual RCA to find the root cause of optimizations for complex modern designs can be inefficient and ineffective.

Finding root causes of such synthesis optimizations with fan-in spanning across several layers of hierarchy makes the debug even more difficult. Using combined structural and formal RCA techniques in an RTL signoff solution, Implementation Design Check (IDC) analysis can group violations by root cause and optimization type. This speeds debug to find reasons for optimizations that don’t meet the design intent.

Early design analysis solution

All five of these trends in RTL signoff are reflected in the latest generation of the Synopsys VC SpyGlass family of early design analysis tools. This solution represents the third generation of RTL signoff. As shown in the figure below, the first two generations focused on delivering scale, efficiency, and ease of use to match handling of growing design complexity over the years with multiple applications such as basic lint, CDC, RDC, and early RTL testability analysis (in conjunction with Synopsys TestMAX Advisor).

Third-generation RTL signoff has many new capabilities, including advanced lint checks, identification of glitches that may impact design functionality, power and congestion analysis, and IDC. Functional CDC is performed on the RTL design, and results are fed to the CDC-aware implementation tools so that synthesis does not cause resurfacing of old CDC problems, followed by incremental yet automated netlist CDC signoff. This RTL signoff flow represents the hyperconvergence of RTL signoff flows with implementation for shift left and zero bug escapes.

Summary

Signoff at the RTL stage is a key part of shifting left the chip development process. A simple RTL signoff process has evolved into a wider array of RTL analysis capabilities. Most errors can be found and fixed in the pre-synthesis code, and the ensuing flow is carefully engineered not to break the design. With third-generation RTL signoff, first-silicon success is feasible for chips of ten billion gates and more, including multi-die designs.

Rimpy Chugh is a principal product manager at Synopsys.