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Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications


Abstract:  "The expansive globalization of the semiconductor supply chain has introduced numerous untrusted entities into different stages of a device’s lifecycle, enabling them to compromise its security. To make matters worse, the increasing complexity in the design as well as aggressive time-to-market requirements of the newer generation of integrated circuits can lead either designers t... » read more

Comparing And Spotting The Difference Between Two Simulations


Comparing is a basic skill we all use in our daily lives in order to understand reality and analyze situations. When it comes to chip verification, the fundamental task of checking also involves comparing because checking is always "checking vs. something" — the ASIC specification and/or a model. In practice, when we encounter a failing test, oftentimes we have a comparable passing tes... » read more

Adaptive NN-Based Root Cause Analysis in Volume Diagnosis for Yield Improvement


Abstract "Root Cause Analysis (RCA) is a critical technology for yield improvement in integrated circuit manufacture. Traditional RCA prefers unsupervised algorithms such as Expectation Maximization based on Bayesian models. However, these methods are severely limited by the weak predictive capability of statistical models and can’t effectively transfer the yield learning experience from old... » read more

Machine Learning Enabled Root Cause Analysis For Low Power Verification


By Himanshu Bhatt and Susantha Wijesekara Next-generation SoCs with advanced graphics, computing and artificial intelligence capabilities are posing unforeseen challenges in verification. Designers and verification engineers using static verification technologies for low power often see many violations in the initial stages. Efficient debugging and determining root cause is a real issue and ... » read more

The Debug Problem…


While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. New algorithms including machine learning, visualization approaches, and problem-solving ideas allow a different approach to debugging that saves up to an order of magnitude in debug time. Since the inception of Hardware Desc... » read more

Failure Analysis of a Product—Not Only a Component


Classic failure analysis (FA) technique generally deals with a single failed component in a complete product to detect the root cause of failure. This approach is inexpensive and less time-consuming. However, this may end up with a wrong interpretation of the product failure or overlooking the synergetic effect of different components related to the failure. This article is about a product on ... » read more

Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis


Abstract As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, ... » read more

Debugging Debug


There appears to be an unwritten law about the time spent in debug-it is a constant. It could be that all gains made by improvements in tools and methodologies are offset by increases in complexity, or that the debug process causes design teams to be more conservative. It could be that no matter how much time spent on debug, the only thing accomplished is to move bugs to places that are less... » read more

Debug: Last Bastion Of Automation


There have been a number of times when anecdotal evidence became folk law and then over time, the effort was put in to find out whether there was any truth in it. Perhaps the most famous case is the statement that verification consumes 70% of development time and resources. For years this “fact” was used in almost every verification presentation and yet nobody knew where the number had come... » read more

Automating Root-Cause Analysis To Reduce Time To Find Bugs by Up To 50%


If you’re spending more than 50% of your verification effort in debug, you’re not alone. For many design, verification, and embedded software engineers as well as engineers verifying complex standard protocols, debug is the primary bottleneck in verification. Most debug today is completed using the traditional methodology of print statements paired with waveforms. Given that today’s desig... » read more

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