Criticality of Wafer Edge Inspection and Metrology Data to All-Surface Defectivity Root Cause and Yield Analysis

Edge yield issues are a growing problem, but a cluster inspection platform could improve production monitoring.

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Abstract
As device sizes continue to increase on devices at 2x nm design rule and beyond and high wafer stress is worsening due to multi-film stacking in the vertical memory process, we observe an increasing trend in edge yield issues worldwide. Wafer edge inspection and metrology become thus critical to drive root cause analysis for improving the yield during a new technology ramp. Nowadays, wafer defectivity correlation to edge is also key for production monitoring, but not without challenges due to the diverse sensitivity demands for the wafer front side, as compared to the wafer edge and back side.

In this paper we are able to demonstrate that a cluster inspection platform with the proper balance of sensitivity and throughput is a key enabler for production monitoring. The study required high resolution imaging of the wafer front side, accurate metrology and defect binning capability at the wafer edge, and unique capability to isolate issues that matter in the wafer backside – all in a single inspection cluster tool platform. This setup allows for faster time to decisions and eliminates the need to rely on other sources of inspection data.

We present several examples of defectivity correlation between the wafer edge and both front and back side, with scanning electron microscope (SEM) examples showing same defect types captured. The root cause for edge defectivity is very often found to be in the crossover of edge beam removal (EBR) lines from successive steps. High-quality and accurate EBR metrology is thus essential on many process steps including on backend layers where many EBR lines are found and need to be distinguished. Likewise, anomalies in metrology data of the edge profile can also act as an important indicator of possible defectivity on the wafer.

I. Introduction
The semiconductor industry’s constant focus is on overall yield improvement. For advanced memory and logic devices at 2x nm and smaller design rules, edge yield is a major factor for increasing device yield and Fab productivity. Edge die yield is becoming even more critical as semiconductor manufacturing Fabs attempt to save costs by reducing the wafer edge exclusion to produce a larger number of yielding die per wafer. As a consequence, wafer edge defect inspection and metrology applications are now critical components of the overall yield management strategy in advanced semiconductor Fabs.

Nowadays, in order to shorten ramp-up time when new devices at 2x nm design and beyond are being developed, the predominant trend for production Fabs has been to implement new device and processes shortly after they have been developed in R&D. However, the learning and research to find viable solutions to improve edge yield have been very slow and painful because of complex processes like multi-film stacks, vertical integration and photolithography, an area most affected by defect formation at the wafer edge because of the continuous evolution in process and materials. Some of the underlying reasons for the slower edge yield learning are as follows: 1) Lack of obvious root cause; 2) Lack of proper control & monitoring methodology; 3) Lack of focus on edge yield during R&D phase; 4) Lack of committed resources.


Fig. 1. Comparison of Center vs. Edge Yield trend during a new device ramp as a Function of Time

We are collaborating on developing a robust solution for edge yield issues affecting all of the wafer surfaces (Frontside, Edge and Backside) through a new Edge Yield Inspection cluster tool (KLA-Tencor’s CIRCL). We have performed a very successful wafer demo test on CIRCL to discover some of the root causes contributing to wafer frontside particles on Film deposition and Etch processes. Demo results have shown good edge monitoring capability with high sensitivity and throughput, uniquely enabled by high quality, custom developed optical systems and through advanced application features. We are currently working to continue the collaboration on site by jointly developing more comprehensive and systematic edge yield solutions by implementing novel features on the CIRCL platform.

In order for advanced semiconductor fabrication processes to be successful at smaller design rules, it is necessary to analyze edge yield issues during the course of fabrication for both process development, where baseline reduction is the primary focus, and production monitoring, where excursion control becomes the priority. Through our collaboration we will be investigating critical edge yield issues and developing good solutions to satisfy both use cases.

II. Discussion
A. Background
In fabrication processes at smaller design rules, there are a lot of edge issues causing edge yield loss. The following are key issues for each process:
a. Photo process: Edge Defocus, Edge Particles/Residues, Edge Overlay & CD Variation, Abnormal EBR Traces. WEE Process
b. Etch process: Bevel Etch and edge roughness particles and residues issues
c. Film Deposition and coating process: Wafer Centricity issue, Abnormal Coating, multi film deposition
d. Cleaning process: Particles, peeling, residues
e. CMP process: Bevel chipping, CMP deep scratch damage, Film Peeling
f. Other: Warpage, Edge Profile issue

In this study, we prepared two demo test wafers. We investigated Film deposition process and Bevel Etch process through a wafer demo test on KLA-Tencor’s CIRCL cluster platform. SiGe film deposition process is very important on DRAM device’s process. SiGe material is used to make upper electrode plate of Capacitor (Storage Node).


Fig. 2. Capacitor Top Plate (SiGe): Vertical/Horizontal SEM Image (from Ref [7])

During the SiGe film CVD deposition process, one dummy bare wafer on the top slot (Slot#25) is used for the rest of the production lot consisting of 24 wafers. This dummy bare wafer is recycled and used several times. Because this dummy bare wafer is used several times, several layers will be deposited on all its surfaces (front side, edge and backside). In some cases, contamination issues will occur on the remaining product wafers (24 wafers) due to peeling issues occurring at the wafer edge region of dummy bare wafer (Slot #25). Those particles caused by wafer edge peeling in turn affected successive process steps and ultimately caused serious edge yield loss. It is therefore an imperative to determine the root cause of these particles and the onset of peeling defects on the dummy wafer. It is also important to understand how peeling defects are spread to frontside and backside surfaces. Currently monitoring these issues is done by manual operators with all its idiosyncrasies. The goal is to find an automated solution to monitor this edge peeling issue and how peeling particles spread to product wafer front and back side.


Fig. 3. Example of Peeling Defect on Slot#25 Dummy wafer

Bevel Etch process is very important to clean wafer edge region. Sometimes when Edge Bevel Etch process for Storage Node Oxide is performed on etch process tool, peeling issues also occur and the resulting particles will spread to the wafer frontside and backside surfaces. Here also an automated solution is needed to monitor wafer edge regions for defectivity and EBR (Edge Bead Removal) trace & Edge Profile after Oxide Bevel Etch process.


Fig. 4. Wafer Edge image after Oxide Bevel Etch (Optical Image)

B. Demo study
KLA-Tencor’s CIRCL Cluster platform was used for a wafer demo. The configuration of CIRCL5 Cluster tool has multiple modules including Frontside Inspection, Edge Inspection & Metrology, Backside Inspection and a dedicated module for Review & Metrology (Fig. 4).
The 8920 is frontside inspection module, a high-throughput monitoring solution capable of sub-180nm defect size capture and 2D metrology measurement applications.

The BDR backside inspection and review module is a high-throughput monitoring solution for the wafer backside defect detection also featuring accurate binning and spatial signature analysis (SSA) defect post-processing algorithms dedicated to process tool chuck fingerprinting.

The CV350 module is the best-in-class technology for high-throughput edge production monitoring, with 125nm sensitivity defect detection and EBR Metrology & Edge Profile capability.

The micro module is dedicated for automated high-resolution defect review and 2D & 3D spotcheck metrology capability.


Fig. 5. KLA-Tencor’s CIRCL Cluster platform

The demo test was completed with two demo wafers on KLA-Tencor’s CIRCL Cluster platform: the first test wafer was for the SiGe film deposition use case demonstration while the second test wafer was for the Oxide Bevel Etch use case demonstration.

The demo wafer for first test item was an actual dummy bare wafer reused several times during the standard SiGe film CVD process. This wafer was found to have many peeling defects at the wafer edge region. For the demonstration we followed the procedure described in Fig. 6.


Fig. 6. Demo procedure on KLA-Tencor’s CIRCL Cluster platform

Based upon the defect detection data on CV350, the peeling/scratches issue defect could be detected with good wafer map trend, showing high sensitivity in detecting smaller DOI (<0.5um). It was easy to achieve automatic defect binning with iDO/RBB with Accuracy >90%, captured good defect image with high quality and it was easy and fast to set up test recipe. On Edge Metrology test, two EBR traces were detected with a single panoramic image (TS/SS/BS) through high quality image with good focus tracking throughout (Fig. 7).

We developed a good use case for defect inspection and multi EBR trace line detection. This will be very useful to monitor wafer edge issues in an automated fashion.


Fig. 7. Defect Inspection and EM data of SiGe wafer on CV350


Fig. 8. SEM image of Edge Cluster particles detected from CV350

On the Edge Profile parameter data of CV350 results, high quality & resolution Edge Profile images were captured and several EP parameters calculated and trend charts generated reporting information of Wafer Thickness, Shoulder radius, Apex length, Bevel Angle, Apex Angle (Fig. 9). The data shows good reliability and stability of edge profile parameter data, and correlation between defect map/EM data and EP parameter data could be established. It was very useful to analyze wafer edge shape and profile Z-cut information. Especially, will be very helpful to monitor edge bevel etch process and multi-film stack deposition or Photo Litho process.


Fig. 9. Edge Profile Parameter data of SiGe wafer on CV350

On the Defect detection data of BDR300 results, peeling defects could be detected and high-quality overview images were generated. Through the backside Color Overview images we were able to demonstrate a use case for monitor wafer backside film deposition status. This BKM will be applied for production monitoring on the CIRCL5.


Fig. 10. Backside inspection data of SiGe wafer on BDR300

On the 8920 frontside inspection module, peeling defects could also be detected on the frontside region close to the edge and high-quality overview images were collected. Through the iDO feature (inline Defect Organizer), we were able to prove good binning accuracy (>90%). Main sizes detected were small defects under 0.5um. Through this data, we discovered that FS inspection requires higher sensitivity to detect smaller size defects (<0.5um), while the Color overview image data can be used to monitor effectively wafer surface status after Photo Litho, Film deposition and CMP processes.


Fig. 11. Frontside inspection data of SiGe wafer on 89xx

The 8920 module detected many peeling particles on the frontside surface. The smallest defect detected was 155nm size defects as shown in this SEM image:


Fig. 12. SEM image of Small particles detected by the 8920 frontside module

The demo wafer for second test item was real oxide bare wafer made from Oxide deposition and Bevel Etch processes And this wafer had many particles and residues defect on wafer edge region.

On the Defect detection data of CV350 results, we could detect the issue defects (peeling/scratches) with good wafer map reporting showing high sensitivity values to get high defect density because this process was to be oxide bevel etch process. It was easy to achieve automatic defect binning with iDO/RBB with Accuracy >90%. We captured good defect image with high quality and fast recipe setup. On the Edge Metrology test, detected 8ea Multi EBR Traces with one Panorama image (TS/SS/BS) through high quality image and good focus. (Fig. 12). We got good Use case about how to deal with Defect Inspection data and Multi EBR Trace lines. This will be very useful to monitor wafer edge issues after Bevel Etch process.


Fig. 13. Defect inspection and EM data of Bare Oxide Bevel Etch wafer on CV350


Fig. 14. SEM image of Small particles detected from CV350

On the Edge Profile parameter data of CV350 results, we were able to capture high quality Edge Profile image and got several EP parameter trend charts with Wafer Thickness, Should radius, Apex length, Bevel Angle, Apex Angle. Especially, we established that trend chats of Shoulder Radius and Apex Length parameters are good for monitoring edge shape and profile after oxide bevel etch process. Those EP data were very useful to do wafer edge shape analysis and to discover edge issues (Fig. 15). The data also proves good reliability and stability of edge profile parameter data. Through this data, could do some correlation between defect map/EM data and EP parameter data. Analysis of wafer edge shape and profile Z-cut information was determined to be highly useful. Through those EP data, we got good BKM about how to deal with this data and how to monitor Edge Profile.


Fig. 15. Edge Profile Parameter data of Bare Oxide Bevel Etch wafer on CV350

On the Defect detection data of BDR300 results, could detected high defects with high defect density and good defect map trend on wafer backside edge region, with high quality overview images. We got good use case to monitor wafer backside film deposition status through those Backside Color Overview images. Will apply with this BKM for production monitoring.


Fig. 16. Backside inspection data of Bare Oxide Bevel Etch wafer on BDR300

On the Defect detection data of 89xx results, could detected peeling defects with good defect map trend on wafer frontside edge region. With iDO (inline Defect Organizer), got good accuracy (>90%). Main sizes detected were small defects under 0.5um.

Through this data, we have discovered that FS inspection needs to have higher sensitivity to be able to detect smaller size defects (<0.5um) and that Color overview image data will be useful to monitor wafer surface status after Photo Litho, Film deposition, CMP process.


Fig. 17. Frontside inspection data of Bare Oxide Bevel Etch wafer on 89xx


Fig. 18. SEM image of Small particles detected from 89xx

C. Data Correlation Summary
We have tried to do some correlation analysis about each Defect inspection data of each modules about SiGe demo wafer. Found out good correlation and matching defect map trend data between CV350 and 89xx / BDR300 on several theta areas. Have confirmed that Edge Peeling defects were spread to frontside and backside area. Finally those cluster locations of those particles by edge peeling are found to be highly correlated between edge and frontside/backside as root cause for many particles of wafer top- and back-side contamination (Fig. 19).

We have tried to do some correlation analysis about each Defect inspection data of each modules about Oxide Bare Bevel Etch demo wafer. Found out good correlation and matching defect map trend data between CV350 and 89xx / BDR300 on two theta regions (Point#1, 3). Point#2 region was Dropped Particles. Have confirmed that Edge Peeling defects were spread to frontside and backside area. Finally those cluster locations of those particles by edge peeling are found to be highly correlated between edge and frontside/backside as root cause for many particles of wafer top- and back-side contamination. (Fig. 19)


Fig. 19. Defect Correlation data of All-surface Wafer Map Overlay on CIRC5 (89xx, CV350, BDR300) about SiGe wafer


Fig. 20. Defect Correlation data of All-surface Defect Wafer Map Overlay on CIRC5 (89xx, CV350, BDR300) about Oxide Bevel Etch wafer

D. Demo BKM
Based on the good performance demo results achieved with KLA-Tencor’s CIRCL Cluster platform. We could do the real data analysis and definition of the root cause about Edge issues on wafer edge region through two wafer demo test. We established a BKM (Fig. 21) about how to do wafer inspection and how to collect data and correlation analysis through the collection data from CIRCL and got good use case to apply with BKM analysis of multi-EBR Trace lines and EP data. Especially, we have collected all inspection and Edge Metrology data from those wafer demo test on CIRCL. We thought that Cluster tool need to apply for production monitoring to define various edge issues on time. We could do multi defect map correlation with one CIRCL cluster tool. The CIRCL platform uniquely offers DirectedSampling and FS/BS defect correlation features to render root cause discovery of several issues much easier to accomplish.


Fig. 21. Root Cause Analysis and Correlation BKM

III. Conclusions
The semiconductor industry continues to have some limitation to move rapidly into the production ramp for high technical devices with Smaller Design Rule due to the technical challenges that are now faced to Edge Yield issues. In this paper, we confirmed good use cases and BKMs about how to deal with edge yield issues as demonstrated on KLA-Tencor’s CIRCL Cluster platform. Through those demo results, we established that high sensitivity and high throughput tool are both necessary ingredients to quickly discover the root cause of edge issues, which then leads to better Edge Yield management. We showed proof that the CIRCL tool has adequate capability to monitor edge issues with good productivity, even in the presence of complex and varied edge issues caused by multiple film stacks and smaller design rule. We developed viable solutions to cover several use cases as part of the demo study that was conducted. We have established good performance data and productivity capability on CIRCL and we will continue to develop new features as part of the CIRCL roadmap to provide further enhancements to our solutions for edge yield in a mutual collaboration between SK hynix and KLA-Tencor.

References

  1. Marlene Strobl, “Immersion Lithography process improvements by wafer edge inspection at 300mm DRAM Manufacturing fab”, 2010 International Symposium on semiconductor Manufacturing (ISSM), pp. 1-4, 2010.
  2. K. Wong, “Development of new methodology and technique to accelerate region yield improvement”, Advanced Semiconductor Manufacturing Conference and Workshop (ASMC), pp. 82-85, 1998.
  3. Oguz Yavas, ”Wafer-edge yield engineering in leading-edge DRAM manufacturing”, FT39-02_4 on FabTech.
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Authors
TaeHui Kim, JaeHyoung Oh, HyungWon Yoo of SK Hynix Semiconductor Inc.
DoOh Kim, Tommaso Torelli of KLA-Tencor Corp.

As published in the Proceedings of the SEMI Advanced Semiconductors Manufacturing Conference (ASMC 2016), May 16-19, 2016, Saratoga Springs, New York.



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