Shift Left Verification With Comprehensive Lint Signoff

With soaring complexity and continuously increasing chip sizes, achieving efficient and predictable design closure has become a prominent challenge among designers today. Demand for a faster time to market is forcing designers to find ways to shorten design cycles with accurate, efficient, one-time RTL to silicon. To meet these requirements designers are looking to implement early ”shift left... » read more

ROI Not There Yet For SysML

At some point down the road in the realm of system-level design, the Systems Modeling Language (SysML) dialect of the Unified Modeling Language (UML) standard may drive into semiconductor design. So far, however, a return on investment has not been established for its use. SysML is defined as a general-purpose visual modeling language for systems engineering applications, and it supports the... » read more

Do SoCs Need Earthquake Insurance?

RTL sign-off is not a new term, but with SoCs that can be comprised of up to 90% IP blocks combined with the complexities that advanced manufacturing process nodes bring, RTL sign-off activities become a process that demands a more comprehensive approach. “There is a fundamental shift going on in chip design in general in that there is a bigger focus on so-called system on chip (SoC) desig... » read more

DAC Is Where?

By Mike Gianfagna DAC season is upon us. I gave up counting the number of DACs I’ve attended a long time ago—when I turned 29 for the third time, I believe. This year, DAC is special in a few important ways. First of all, it’s the 50th DAC. Yes, the show has indeed been around that long. It started as a workshop with a bunch of engineers debating algorithms. For an industry that is arg... » read more