Top Stories

Inside Intel’s Ambitious Roadmap
Five process nodes in four years, high-NA EUV, 3D-ICs, chiplets, hybrid bonding, and more.

Angstrom-Level Measurements With AFMs
Atomic force microscopy is playing a bigger role as critical dimensions shrink and more chips are assembled in packages; competition is growing.

Stacked Nanosheets And Forksheet FETs
Next-gen transistors will continue using silicon, but gate structures and processes will change.

Current And Future Packaging Trends
Experts at the Table: Rising costs and the physical limits of reticles is forcing more companies to examine alternatives to shrinking geometries.

Blogs

Executive Editor Mark LaPedus talks with Semico Research’s CEO about changes in the memory biz, in What’s Ahead For DRAM, NAND?

Coventor’s Michael Hargrove looks at how nanosheets stack up to finFETs, in Advancing To The 3nm Node And Beyond: Technology, Challenges And Solutions.

Calibra’s Jan Willis examines the use of variable-shape e-beam (VSB) photomask writers in writing curvilinear shapes, in Optimizing VSB Shot Count For Curvilinear Masks.

JCET’s Ken Hsiao lays out different options and benefits for different applications, in Ultra-Small Fan-Out Packaging Solution.

Lam Research’s David Haynes traces the impact of specialty technologies such as MEMS, CMOS image sensors, and RF devices on everything from smartphones to COVID-19 testing, in Specialty Technologies Bring New Functionality.

Amkor’s Curtis Zwenger finds a growing number of new frequencies and multiplexing methods have increased the complexity of the RF front end, in Empowering RF Front End Cellular Innovations With DSMBGA.

TechInsights’ Jeongdong Choe tears down 176L 3D NAND to reveal changes as the number of layers increase, in Micron B47R 3D CTF CuA NAND Die, World’s First 176L (195T).

Sponsor White Paper

Marangoni Effect-Based Under-Layer For A Dual Damascene Via-First Approach
A scalable solution to the unwanted photoresist swing effect.

Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS
The benefits of WLFO versus flip-chip land grid array (FCLGA) packaging for a radio frequency (RF) MEMS digital tunable capacitor array.

Process Variation Analysis Of Device Performance Using Virtual Fabrication — Methodology Demonstrated On A CMOS 14-Nm FinFET Vehicle
A new methodology to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance.

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