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Wafer-Level Fan-Out For High-Performance, Low-Cost Packaging Of Monolithic RF MEMS/CMOS

The benefits of WLFO versus flip-chip land grid array (FCLGA) packaging for a radio frequency (RF) MEMS digital tunable capacitor array.

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Navigating the trade-offs between performance, size, cost and reliability can be a challenge when considering integrated circuit (IC) packaging and the end-application. The integration of micro-electromechanical systems (MEMS), either monolithic or heterogeneous, introduces yet another level of complexity that has only recently been a major focus of multi-device packaging [1]. Wafer-level fanout (WLFO) technology can enable improvements in several areas, primarily the reduction in size of parasitic interconnects and, proportionally, a drastic decrease in overall form-factor as compared to more ubiquitous chipscale packaging solutions. Widespread adoption of WLFO packaging [2] has driven implementation costs to a level competitive with traditional fan-in wafer-level packaging.

This study quantifies the benefits of WLFO versus flip-chip land grid array (FCLGA) packaging for a radio frequency (RF) MEMS digital tunable capacitor array integrated with 180nm CMOS technology. RF performance hinges critically upon the ability of the package to transfer signals with minimal impedance, necessitating shortened redistribution layer (RDL) paths and reduced, or removed, solder interconnects. Flip-chip packaging requires a multilayered substrate and an intermediate solder interconnect while chip-first WLFO packaging makes use of direct Cu RDL bond to die pads and a single-level of routing to the ball grid array.

Click here to read the paper.

Authors:
Rameen Hadizadeh, Anssi Laitinen and David Molinero, Ph.D.
WiSpry, Inc.
Irvine, CA, USA

Nelson Pereira and Márcio Pinheiro
Amkor Technology, Inc.
Porto, Portugal

 



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