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Micron B47R 3D CTF CuA NAND Die, World’s First 176L (195T)

Teardown of 176L 3D NAND reveals changes as the number of layers increase.

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Micron’s 176L 3D NAND is the world’s first 176L 3D NAND Flash memory. TechInsights just found the 512Gb 176L die (B47R die markings) and quickly viewed its process, structure, and die design. Micron 176L 3D NAND is one of the most groundbreaking technologies to date, and it is especially for the storage application such as data center, 5G, AI, cloud, intelligent edge, and mobile devices. Micron already announced its performance improvement, for example, read latency and write latency improved by more than 35% from 96L FG CuA, and over 25% from 128L CTF CuA.

We tore-down Micron 3400 1TB SSD (PCIe Gen-4 cSSD NVMe 1.4) and got the MT29F4T08EQLEEG8-QB: E (FBGA Code: NY124). Two 512Gb devices are packaged on the board for 1TB SSD. The 3400 SSD uses Micron’s latest in-house SSD controller, DM02A1, which is different from previous 2300 SSD (96L) and Crucial P5’s DM01B2 controller.


Fig. 1: Micron 176L 512Gb TLC die images; top metal viewed and CuA viewed (die markings added).

Figure 1 shows a top metal viewed die, a CMOS circuitry viewed die, and B47R die markings. In comparison with previous 128L CTF CuA 512Gb B37R TLC die, die size decreased by 25% due to higher cell density, increased 3D NAND cell numbers, and page buffer/wordline switches design scaling effectively.


Fig. 2: Micron 3D NAND architecture and vertical NAND string height trends up to 176L.

The 176L 3D NAND is the 2nd generation CTF structure for Micron (figure 2). The NAND cell array height (the height from source-side selector to BL, for comparison) is now more than 11 µm. Total number of gates including selectors (STs) and dummy word lines (DWLs) per vertical NAND string is 195, 195T so called, which is the highest number ever on 3D NAND (figure 3). They keep double stack architecture, replacement-gate process, charger trap nitride (CTN), and CMOS-under-Array (CuA) techniques.


Fig. 3: A comparison of total number of gates for 3D NAND players and devices.

Bit density reached to 10.273 Gb/mm2 for 512Gb TLC die by substantially shrinking the die size compared with previous 128L 512Gb TLC die (B37R die markings, 7.755 Gb/mm2. It’s the world’s first TLC NAND die with more than 10 Gb/mm2 density (figure 4).


Fig. 4: Micron 512Gb TLC NAND die size and bit density trends, up to 176L.

In comparison with Micron 128L, the new 176L cell structure consists of two decks with 88 WLs for each. Interconnection metals and contacts/vias for BEOL and CuA are the same with 128L, while vertical channel (VC) hole height increased to 10.6 µm. 3D NAND unit cell size in WL and BL directions keeps 0.02 µm2, while unit cell volume slightly decreased to 1.12 x 10-4 µm3 due to a smaller gate pitch (Table 1).


Table 1: A comparison of device features, Micron 512Gb 128L vs. 176L.

As the number of cell gates increase beyond 150L, we expect a lot of challenges are there, for example, alternative layers stacking (mold layers), WL staircase optimization, vertical channel hole HAR etching and ALD layer process, ONO cut, deck misalign, sacrificial layer removal, replacement gate fill, CSL trench profile, wafer warpage, and related process uniformity. We’ve been looking through the successfully commercialized 176L devices.



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