Special Report
Everyone’s A System Designer With Heterogeneous Integration
Engineers are encountering more unknowns, working with different people and tools, and focusing on new types of tradeoffs.
Top Stories
Anatomy Of A System Simulation
Balancing the benefits of a model with the costs associated with that model is tough, but it becomes even trickier when dissimilar models are combined.
Rethinking Design, Workflow For 3D
The semiconductor ecosystem is coping with new challenges in the transition to 3D advanced packaging.
Making Connections In 3D Heterogeneous Integration
New packaging options are stacking up, but taking advantage of them isn’t easy.
Navigating EDA Vendor Cloud Options
Cloud costs and challenges, and working with multi-vendor tools in cloud environments.
What Will That Chip Cost?
Establishing the true cost to develop an advanced chip is complicated, but headline numbers appear to be significantly inflated.
Videos
Verifying A RISC-V Processor Model
What’s different from other RISC-V designs and what’s needed to ensure it works as planned.
Memory And High-Speed Digital Design
Safeguarding signal integrity with new and faster versions of DRAM.
DSP Techniques For High-Speed SerDes
What’s needed in chip design to handle an explosion in data.
Blogs
Technology Editor Brian Bailey cautions that understanding what can go wrong is even more essential when AI is involved, in The Limits Of AI-Generated Models.
Synopsys’ Yervant Zorian emphasizes the importance of thorough testing from die to system and how silicon lifecycle management helps complex designs work as intended, in Ensuring The Health And Reliability Of Multi-Die Systems.
Arteris’ Frank Schirrmeister explains how control and status register mismanagement can lead to expensive oversights, in System-On-Chip Integration Complexity And Hardware/Software Contracts.
Movellus’ Barry Pangrle points to two big technology advancements and what they mean, in Leaps In Quantum Computing.
Codasip’s Roddy Urquhart warns that memory safety vulnerabilities are a significant proportion of those reported and are growing in number, in Causes Of Memory Unsafety.
Cadence’s Steve Brown shows how generative AI tools could boost design exploration and predictive analysis, in AI For Circuit Design Quality, Productivity, And Advanced-Node Mapping.
Siemens EDA’s John Ferguson calls for doing physical verification as early as possible in the design flow and continuing to check throughout the process, in Let’s Do The (IC Design) Time Warp Again.
Keysight’s Hwee Yng Yeo finds the route for meeting the needs of electrified trucks and buses starts at the battery cell chemistry level, in Powering Up Electric Heavy-Duty Vehicles.
Expedera’s Paul Karazuba explains how training and inferencing at the edge enables AI applications with low latency, enhanced privacy, and the ability to function offline, in Unlocking The Power Of Edge Computing With Large Language Models.
Sponsor White Papers
Selective Radiation Mitigation For Integrated Circuits
A methodology for improved reliability in space.
FIR And Median Filter Accelerators In CodAL
L31 embedded core extensions for wireless and connectivity — Part 2.
ESD Co-Design For 224G And 112G SerDes In FinFET Technologies
Measures to minimize the capacitive load of the protections by developing a transmitter that is intrinsically robust to ESD.
Five Strategies To Accelerate 5G Device Development
Five strategies to help you address these challenges and get your designs to market faster.
Why A DSP Is Indispensable In The New World of AI
The challenge for the SoC architect is to design a chip with an AI inference solution that is flexible for any future neural network not yet invented.
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