Top Story
Chip Design Shifts As Fundamental Laws Run Out Of Steam
How prepared the EDA community is to address upcoming challenges isn’t clear.
Raising IP Integration Up A Level
Integrating IP has never been easy, but it is about to take a big leap in complexity. Identifying the necessary models and abstractions is just beginning.
Fabless IDMs Redefine The Leading Edge
Systems companies are designing and using their own chips, but not everything goes as planned.
Bug-Free Designs
Does anyone really care if a design is bug-free? The cost probably would be prohibitive.
Bespoke Silicon Rattles Chip Design Ecosystem
From specific design team skills to organizational and economic impacts, the move to bespoke silicon is shaking things up.
Video
Testing 2.5D And 3D-ICs
Access to dies or chiplets is problematic, but a new standard may help.
Blogs
Technology Editor Brian Bailey explains why power could become the most important optimization consideration in the future, in A Power-First Approach.
Siemens EDA’s Michael White, with Google Cloud’s Peeyush Tugnawat and AMD’s Philip Steinke, advise how to avoid hitting the on-premises resource wall as compute requirements rise, in Considering The Power Of The Cloud For EDA.
Synopsys’ Dana Neustadter finds that securing high bandwidth interfaces is key to protecting the data that moves across them, in Enabling The Highest Levels Of SoC Security.
Codasip’s Filip Benna points to a burgeoning ecosystem driving a virtuous spiral of choice and innovation, in 5 Good Things About RISC-V.
Renesas’ Roger Wendelken shows why helping customers understand security is so important, in Data Security Takes Front Seat In Industrial IoT Design.
Keysight’s Don Dingee finds that workflows are changing, and design can no longer be an isolated activity, in What Is The Definition Of Design For Context?
Synopsys’ Anand Thiruvengadam, Farzin Rasteh, Preeti Jain, and Jim Schultz apply digital techniques to the memory of the periphery, in Digitizing Memory Design And Verification To Accelerate Development Turnaround Time
Siemens’ Yara Essam delves into improving debug for SoCs and FPGAs, in Debug This! How To Simplify Coverage Analysis And Closure
Sponsor White Papers
Addressing SRAM Verification Challenges
SureCore demonstrates robust low power memory for power critical applications with Solido Variation Designer.
AI-Driven Big Data Analytics Enables Actionable Intelligence, Improving SoC Design Productivity
AI-based tools for analyzing big data in SoC design.
Faster And Smarter LVS For The SoC Era
Some of the challenges and an innovative solution that addresses them.
E-Mobility: Navigate Safety, Interoperability, And Conformance
The current testing and regulatory challenges facing the e-mobility market, and how to overcome them.
AI As A Service For Signal Processing
The technical aspects of an approach to machine learning, and the architecture of Reality Analytics’ solution.
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