AI-based tools for analyzing big data in SoC design.
As the latest systems on chip (SoCs) grow in size and complexity, a vast amount of design data is generated during verification and implementation. Design data is business critical and, with the proliferation of artificial intelligence (AI) use in chip design, provides designers an opportunity to carry forward learnings and insights with every new design. To achieve first-pass success delivering the most demanding chip power and performance goals and to improve engineering team productivity, it is essential this data is utilized more effectively.
The Cadence Joint Enterprise Data and AI (JedAI) Platform harnesses this design data in an open, AI-driven, large-scale data analytics environment, optimized for massive, heterogeneous, structured, and unstructured EDA data. By using the Cadence JedAI Platform, designers can quickly identify the most critical power, performance, and area (PPA) objectives and design bottlenecks, resulting in faster design closure with fewer engineering resources. With the Cadence JedAI Platform, Cadence unifies its computational software innovations in data and AI across the Cadence Verisium™ AI-Driven Verification Platform, to the Cadence Cerebrus™ Intelligent Chip Explorer’s AI-driven implementation and the Cadence Optimality™ Intelligent System Explorer’s AI-driven system analysis. Together, these enable designers to use AI-driven optimization and debug to create multiple designs in parallel with fewer engineers.
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