Top Stories
System State Challenges Widen
The state of a system is fundamental for performing many analysis and debug tasks, but understanding it and its context is a growing challenge.
EDA Pushes Deeper Into AI
AI is both evolutionary and revolutionary, making it difficult to assess where and how it will be used, and what problems may crop up.
3D-ICs May Be The Least-Cost Option
Advanced packaging has evolved from expensive custom solutions to those ready for more widespread adoption.
Videos
Coding And Debugging RISC-V
Customizing designs to improve performance and reduce power.
What To Do About Electrostatic Discharge
Issues multiply in advanced packages and at advanced nodes.
Improving AI Productivity With AI
How engineers can utilize AI to push more design elements further left.
Blogs
Technology Editor Brian Bailey reminisces about working in an industry during its infancy that offered both amazing experiences and challenges, in The Good Old Days Of EDA.
Keysight’s Ben Miller lays out how semiconductor chiplet technology will extend the Moore’s Law benefits of performance and cost while reducing barriers to entry, in Nascent Chiplet Tech Gaining Attention In Defense And Commercial Industries.
Expedera’s Pat Donnelly looks at the generative AI model that is a critical test for NPU design, in Considerations For Accelerating On-Device Stable Diffusion Models.
Siemens EDA’s John Ferguson points to the persistent challenge of using multi-physics to boost 3D-IC performance, in Help, 3D-IC Is Stuck In A Country Song.
Synopsys’ Jim Schultz explains how increasing density makes congestion a challenge for both cities and chips, in A Path To Increase Cell Utilization Rate And Decrease Routing Congestion In Chip Design Floorplanning.
Movellus’ Barry Pangrle considers the use of AI in semiconductor design and its impact on startups, in Artificial Intelligence Wonderland.
Arteris’ Frank Schirrmeister zeroes in on trends shaping chip design and what might be in store next year, in SoC Integration And Data Transport Architecture Requirements Surge In 2023.
Cadence’s Reela Samuel finds that standardized approaches will be needed to ensure that all chiplets work seamlessly together as a unified system, in Building Tomorrow’s Electronics Piece By Piece.
Sponsor White Papers
Accelerate 5G Testing
How 5G technology introduces challenges and requirements that demand sophisticated test capabilities and performance.
The Evolution Of RISC-V Processor Verification: Open Standards And Verification IP
The evolution of RISC-V processor verification methodology using COREV-VERIF as a case study.
Successful 3D-IC Design, Verification, And Analysis Requires An Integrated Approach
Dealing with new challenges along the Z axis.
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