Special Report
The Bumpy Road To 10nm FinFETs
Foundries split over 1D and 2D layout schemes, creating tough choices for chipmakers involving performance, area and other options.
Top Stories
10nm Fab Challenges
Photomask questions, flow changes, new tools and rising costs are raising new questions about when and how to continue device shrinking.
How Hard Is FD-SOI Design?
As 28nm FD-SOI manufacturing technology comes into mass production, what is the impact on the design side?
Waiting For Next-Gen Metrology
Research is underway to supplement or replace existing equipment at 10nm and beyond.
One-On-One: Thomas Caulfield
GlobalFoundries’ general manager for Fab 8 opens up on Moore’s Law, 14nm, 22nm FD-SOI, future investments and stacked die.
Video
Tech Talk: 14nm
Issues and solutions for dealing with finFETs.
Blogs
Editor in Chief Ed Sperling says the future after the next process node is uncertain, which should keep everyone on edge for years to come, in What’s After 10nm?
Executive Editor Mark LaPedus observes that to figure out when 10nm will happen you need to follow the fabs, in 10nm Fab Watch.
Mentor Graphics’ Bill Graupp writes that a well-designed programmable edge modification flow can improve a layout by analyzing a design and removing offending edges, in Automated Chip Polishing Can Make Your Design Shine.
KLA-Tencor’s Zain Saidin takes a 37-year tour of fab equipment to show much has changed in a field many of us take for granted, in Reticle Inspection And Metrology.
SEMI’s Debra Vogler digs into what’s needed at 10nm and below and why, in Next-Gen Metrology: Searching For A Bright X-Ray Source.
White Papers
Addressing Thin Film Thickness Metrology Challenges Of 14nm BEOL Layers
How to model change of copper film properties and what are the proper methods for low-k film thickness measurements in each CMP step.
Next-Generation Parasitic Extraction For 16nm And Beyond
The Calibre xACT platform targets finFET, custom, analog and RF designs at 16nm and below.
