The Bumpy Road To 10nm FinFETs

Foundries split over 1D and 2D layout schemes, creating tough choices for chipmakers involving performance, area and other options.


Foundry vendors are currently ramping up their 16nm/14nm finFET processes in the market. Vendors are battling each other for business in the arena, although the migration from planar to finFETs is expected to be a slow and expensive process.

Still, despite the challenges at 16nm/14nm, vendors are gearing up for the next battle in the foundry business—the 10nm node. At 10nm, foundry vendors are developing a new generation of finFETs.

But based on the early indications, the industry faces some major challenges, if not a bumpy ride, at 10nm. Intel, for one, is pushing out its 10nm finFET production ramp by several months, according to equipment industry sources. On the other hand, Samsung and TSMC are accelerating their respective 10nm finFET efforts. And GlobalFoundries is expected to be in the mix.

For foundry customers, though, the migration toward 10nm finFETs will be a herculean and expensive effort. In fact, it costs four times more to design a 10nm finFET device, as compared to a 28nm planar chip. “These (10nm) designs are going to be expensive,” said Chris Mack, gentlemen scientist and lithography expert. “Only the highest volume producers can afford the next node. There are hundreds of fabless companies that will never do a 10nm design.”

And for other reasons, 10nm could represent a pivotal juncture in the broader foundry business. In fact, the industry could see a bifurcation between vendors in a key area.

TSMC, for one, is moving from a 2D/bi-directional layout scheme at 16nm and above to 1D/unidirectional technology at 10nm. In doing so, the foundry is moving from a relatively flexible design environment at 16nm and above to more restrictive design rules at 10nm.

In contrast, based on early indications, other foundries may continue to follow the more traditional 2D/bi-directional layout path at 10nm, which enables a more flexible design environment for IC designers.

In other words, foundry customers face some difficult choices at 10nm. “These are very complex tradeoffs in terms of circuit performance, circuit areas and options available to the designers,” Mack said.

Still, there is room in the market for both technologies. “Each one has its pros and cons. But you need to make sure whatever solution you provide, the customer has to buy into that,” said Kelvin Low, senior director of foundry marketing for Samsung.

Meanwhile, at a recent event, Samsung rolled out its 10nm finFET technology. The company also showed a 300mm wafer with 10nm finFET transistors. “We have silicon-based PDKs out,” Low said. Samsung plans to move into production with its 10nm finFET technology by the end of 2016, he said.

10nm challenges
Needless to say, there are several unknowns and variables at 10nm. For now, though, the foundries are looking to ramp up 10nm finFETs in volumes around 2017.

The timing, and success, of 10nm finFETs depends upon several factors. To gain any traction, 10nm must keep the industry on the traditional cost-per-transistor curve. “14nm will be a very long node,” said Thomas Caulfield, senior vice president and general manager of Fab 8 at GlobalFoundries. “Then, it comes down to the economics. Will the power, performance and cost at 10nm be a better play than 14nm?”

Indeed, the overriding factor is cost. In fact, the average IC design cost for a 28nm planar device is about $30 million, according to Gartner. In comparison, the IC design cost for a 14nm SoC is around $80 million. “For mid-range 10nm SoC, it takes $120 million for the design cost, plus 60% for the embedded software,” said Samuel Wang, an analyst with Gartner.

On top of that, it could take 300 engineer-years to bring out a 10nm device, Wang said. Therefore, a team of 50 engineers will need six years to complete the chip design to tape-out. In comparison, it takes 100 engineer-years to bring out a 28nm design. And for a 14nm device, it takes 200 man-years, he added.

Besides cost, there are other concerns at 10nm. “One should be concerned about power density,” said Terry Hook, senior technical staff member at IBM. “I am more concerned about power density, getting that current out and really using it.”

On the manufacturing front, meanwhile, there are also several challenges. In theory, a 10nm finFET would consist of the traditional features, such as copper interconnects and high-k/metal-gate. Chipmakers may introduce a more complex germanium mix in the PFET to boost the mobility in the channels.

For patterning, chipmakers will extend 193nm immersion to 10nm. Vendors will also move to triple or quadruple patterning at 10nm, which will be significantly more difficult to master than double patterning at 16nm/14nm.

At 10nm, the current EDA tools can’t account for all of the different colors and possible unknowns. “At 10nm and below, the challenges will be in the tools, the process and the complexity,” said David Abercrombie, advanced physical verification methodology program manager at Mentor Graphics. “We’re seeing more differences between foundries as we move forward, too. At 20nm and 16nm/14nm, it was the same basic layers and simple double patterning. At 10nm, there is more diversity in how they approach multi-patterning. There is still double patterning there, but depending on the layer and the foundry, it might be a completely different experience.”

Unidirectional vs. bi-directional
On this front, each foundry vendor has a different strategy. Intel, for example, used a bi-directional, or 2D, layout scheme at 65nm and above. At those nodes, Intel’s designers enjoyed more degrees of freedom with 2D. But for Intel, 2D designs were complex, if not costly, to fabricate. In 2D, the poly layers are in one direction, while the metal layers are situated in random places.

So, to help simplify the flow for its own chips, Intel moved to 1D/unidirectional layouts, and restrictive design rules, starting at 45nm. In 1D, the metal layers are perpendicular to the other layers.

For Intel, the move toward 1D made sense. After all, the company wants to gain a cost and time-to-market advantage for its own chip products. “Intel was the first to move to restrictive design rules,” said lithography expert Mack. “The advantage of restrictive design rules is that it’s easier to scale, especially from generation to generation.”

Intel also caters to a relatively small group of foundry customers. The question is whether Intel’s ID strategy works in a foundry environment. So far, though, the jury is still out on Intel’s efforts in the foundry business.

Unlike Intel, the other leading-edge foundries have generally followed a somewhat similar 2D/bi-directional strategy. Within reason, foundry customers have enjoyed various degrees of design freedom over the years.

Starting at 10nm, though, foundry vendors could end up moving into one of two camps—1D versus 2D. “We have a choice with some real tradeoffs,” Mack said. “There is a choice between single-direction and single-pitch design strategies, which make compromises and presents some difficulties on the chip design side. But they aid on the lithography patterning side. Then (in 2D), there is more flexibility for a design, but this make the manufacturability far harder.”

The big test case will soon occur at TSMC. At 10nm, TSMC is tweaking its strategy on three fronts. First, after being late to the 16nm/14nm finFET market, TSMC is accelerating its efforts at 10nm. It hopes to move into 10nm risk production by year’s end, with volume production slated by the end of 2016.

Second, TSMC is moving towards a 1D scheme, and restrictive design rules, at 10nm. And third, it is changing its patterning strategy.

At 16nm/14nm, TSMC and other foundries generally use a double patterning process for the critical metal layers. In the fab, the process is called litho-etch-litho-etch (LELE). In LELE, two separate lithography and etch steps are performed to define a single layer, thereby doubling the pattern density.

In LELE, the mask layers are assigned two colors. The mask layers are split, or decomposed, from the original drawn layout into two new layers.

For 10nm, the next logical step is to move to triple patterning or LELELE. In LELELE, the mask layers are assigned three colors.

Triple patterning presents some challenges, however. “The overlay challenges can translate into more variation in the line and space,” said B.J. Woo, vice president of business development at TSMC. “This kind of variation is tolerable for 20nm and 16nm. But for 10nm, this variation will translate to a very small metal space between the metal lines. That could translate into a premature dielectric breakdown.”

Instead of going down the LELELE route, TSMC is moving to self-aligned quadruple patterning (SAQP) for the metal layers at 10nm. SAQP uses one lithography step and additional deposition and etch steps to define a spacer-like feature.

“LELE processes are more expensive and more difficult, as compared to self-aligned double patterning. LELE has very tight restrictions on overlay. Self-aligned processes are not nearly as critical from an overlay perspective,” said lithography guru Mack.

“If TSMC is moving in the [SAQP] direction, that tells me that the manufacturability of multi-patterning lithography is too big of a problem if you don’t impose those unidirectional design rules,” Mack said. “TSMC probably looked at what it would take to print patterns with more arbitrary design styles at 10nm. It could put them out of reach of what is economically feasible.”

Still to be seen, however, is how TSMC’s customers will adjust to a more restrictive design environment at 10nm. “TSMC would not make a decision like this unilaterally. This had to be a cooperative development effort between TSMC and its major customers,” Mack said. “If customers are not happy about it, it’s not because TSMC is making this choice. It’s because life is forcing this choice for them.”

By going the 1D route, though, many foundry customers may face a brave new world. “1D means that once you enforce restrictions, you can control variability,” Samsung’s Low said. “At the same time, you are making the designer’s life much more difficult. You have reduced the degree of freedom of laying out your IPs.”

There are other issues, as well. “If I use restrictive design rules, this allows me to print features at the smallest pitch in one direction. I have some area loss that is caused by the design rule restrictions and the resulting inefficiencies of the layout,” according to Mack.

Still, other foundries may go down the 2D route, which also has some trade-offs. “If I can’t print it, then I have to spread the patterns out to make it printable (as in 2D layouts). That costs area. And area is money,” Mack said.

Which direction will foundry customers go? “By the time we get to the 10nm node, designers must look at which of these two area losses is worse,” he said. “Then, they may pick the one that is not as bad as the other.”

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