One-On-One: Thomas Caulfield

GlobalFoundries’ general manager for Fab 8 opens up on Moore’s Law, 14nm, 22nm FD-SOI, future investments and stacked die.

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Semiconductor Engineering sat down to talk about fabs, process technology and the equipment industry with Thomas Caulfield, senior vice president and general manager of Fab 8 at GlobalFoundries. Located in Saratoga County, N.Y., Fab 8 is GlobalFoundries’ most advanced 300mm wafer fab. What follows are excerpts of that discussion.

SE: Last year, GlobalFoundries licensed Samsung’s 14nm finFET process. What’s the status of the 14nm finFET process running at GlobalFoundries’ Fab 8 facility?

Caulfield: We are in production at 14nm. We are continuing to add capacity as we go at a very brisk pace. We are hooking up 20 tools a week. That’s about as fast as you can run, especially with the level of sophistication of these tools.

SE: Where is GlobalFoundries’ 14nm process in terms of wafer starts?

Caulfield: We project to be at scale over the next three quarters in starts. We are really at the fast part of the ramp. So, I can tell you we are more than 50% of the way in getting all the tools in, but the output of start space is maybe 20% of the ultimate. When we are done, we will have economic scale equivalent to others in the industry.

SE: Is this faster than what you thought?

Caulfield: It’s fast. It’s not faster than we thought. It’s consistent how others ramp large advanced fabs, including our partner Samsung. They are ramping at the same time we are. Samsung is ramping S2 and S1, while we are ramping up Malta. We are collaborating on how we even do the ramps together. We share best practices. We have the same vested interest in making our platform the winning platform in the industry.

SE: Are you running other processes in Fab 8?

Caulfield: We also chose to run 28nm. It’s a technology that we transferred from our Dresden fab. For me, it is very important for the team to get manufacturing discipline. And so we’ve run the 28nm technology very hard. We’ve built in the systems and controls infrastructure for the technology. Our yields are almost at the industry’s best levels at 28nm. We have very good line yields, which is a measure of how many wafers you start and how many are coming out. So we’ve taken 28nm in a very short time to great places. Of course, it’s good to get some revenue against your investment. The real premise of that was to learn and develop a team around manufacturing discipline. So now, as we ramp 14nm, that’s already in place. We just apply chamber matching, fault detection controls and other processes all into 14nm.

SE: What else is going on in Fab 8?

Caulfield: Concurrently, we are doing work on the development side on two technology nodes, such as 10nm. We are also doing the early work on 22nm FD-SOI for a key customer set. And that technology will be ported to our Dresden fab at the end of this year. They will take that technology to volume manufacturing.

SE: Is 22nm FD-SOI a planar technology?

Caulfield: It’s planar, but it’s fully-depleted SOI. You can leverage the 28nm tools and get a power performance value proposition for our customers. Essentially, that gives them a finFET performance at 22nm.

SE: What is the Dresden fab running right now?

Caulfield: Mostly 28nm. It’s both high-k and polysilicon. And it’s a little bit of 32nm.

SE: GlobalFoundries is in the process of acquiring IBM’s Microelectronics Group. Eventually, what will IBM’s fab in East Fishkill run?

Caulfield: I can’t go into great detail on that yet. But the key for Fishkill is to take advantage of a fully depreciated tool set and move development out of Fishkill into Malta, where we have a leading-edge technology. Then we can offer specialty ASICs and RF types of capabilities across various nodes out of Fishkill.

SE: How did you implement Samsung’s 14nm process into Fab 8? Is that a copy exact strategy?

Caulfield: For it to be a truly collaborative and a common platform approach, it has to be almost copy exact. This is because you are committing to your customers a common set of devices, device performances, ground rules and PDKs. So when they make a design, they can make one design and source it at different fabs. So, 90% of it is copy exact. At the end, you can do individual learning to improve the defectivity on your final yield. So, a key part of doing a collaborative effort is to make sure it’s copy exact, so you get a time to market advantage.

SE: What about yields?

Caulfield: When you change architectures and go to a finFET-like device, there is extra learning involved. It takes a bit longer to put it in place. By leveraging Samsung’s work on this, we’re able to introduce the technology after a lot of that work effort has been done. It doesn’t mean that the technology is completely settled. But we are much further along than if we were pioneers and doing this alone.

SE: Can you comment on the yields at Fab 8?

Caulfield: Our yields are exactly where they have committed to be at this point in the program. What you do is run a baseline process. You put the improvements in. You don’t change your baseline until you’ve demonstrated that the improvements work. And we’ve seen those lots come out at a higher yield than the baseline. We’ve been seeing that now since the beginning of this year.

SE: When will 14nm go into volume production in Fab 8?

Caulfield: We will have full capability in starts by the end of Q1 next year.

SE: To start a leading-edge fab, you recently said that it costs around $12 billion. Is that the case?

Caulfield: That’s just for the manufacturing. You still need to spend money for R&D.

SE: Any thoughts on EUV?

Caulfield: ASML and partner companies have all invested a tremendous amount of money in EUV. It’s a very, very difficult technology. But I’m bullish that the industry will find a way there. It needs to certainly get below 7nm or 8nm. I don’t think there is an optical path below that. There may be an optical path to 7nm or 8nm, but it will require very complex patterning, such as triple or quadruple patterning.

SE: When will the industry insert EUV?

Caulfield: There are some who are trying to introduce it at certain critical levels early, perhaps 10nm and certainly 7nm.

SE: What about 10nm?

Caulfield: 10nm will happen. What happens in this industry is that everyone thinks these things will happen a lot sooner than they actually do. 10nm will be another very difficult node to execute. But from an investment perspective, 85% to 90% of the tooling is comparable. You might need a software upgrade or a chamber enhancement. You’ll need more lithography. There will be more triple patterning involved. So the complexity is higher.

SE: Today, the foundries offer 28nm and above processes. Some offer 14nm. And soon, vendors will have 10nm. How will all this play out?

Caulfield: 28nm will be a long-running node, because of the power performance for certain applications. We view 22nm FD-SOI as a great cost performance play, where you get finFET-type performance at 22nm and at 28nm cost. 14nm will also be a very long node. There are a lot of leading-edge designs at 28nm. They will skip 20nm and come in at 14nm. Then, it comes down to the economics. Will the power performance cost at 10nm be a better play than 14nm? And how soon can that be realized if you migrate from 14nm to 10nm?

SE: We’ve seen a lot of consolidation in the equipment industry. Any thoughts?

Caulfield: You need an industry that can create enough value, so they can continue to drive innovation. So what do semiconductor companies like Intel Corp., TSMC, GlobalFoundries and Samsung need? We need a healthy equipment industry. They need to spend in terms of R&D. You need competition. You can over-consolidate, but that is very difficult to have happen. But what consolidation allows for is the ability to leverage investments.

SE: The proposed Applied-TEL merger did not go through and was ultimately terminated. What does that mean for the industry?

Caulfield: The industry could have gained something by leveraging the R&D investments from the two companies in a more focused fashion. They spent 18 months thinking about coming together. But now, they have to reset. That’s going to slow everybody down. I wish the decision could have been reached a lot faster.

SE: Chipmakers want an endless list of new tool technologies, such as EUV, high NA EUV, actinic mask inspection and so on. Who should pay for the R&D?

Caulfield: The perfect example is ASML. Companies came in and invested in them. They used that money to do development. Competitors funded an equipment company to go create a patterning capability for the future. That’s the perfect example of the kind of collaboration the industry needs. Now, having said that, the equipment industry also has a model in which they do a lot of the investment.

SE: Are there enough R&D dollars in the industry to do everything?

Caulfield: This comes back to the point of why you need consolidation and collaboration. You need to leverage those R&D dollars. Imagine spending the same dollars, but you are doing redundant work in two different places. You need clever ways of doing collaboration, because there are only a fixed amount of R&D dollars.

SE: Some see a path to 5nm and 3nm. Can anybody afford to design chips at these types of nodes?

Caulfield: The only way it works is if the cost per transistor decreases generation after generation. There is a set of customers at the leading edge. And at every turn of the crank, driven by mobile computing, they are the first ones at the node driving the performance and leveraging that value proposition.

SE: Will 2.5D/3D advanced stacked die ever happen?

Caulfield: These things are always projected to happen a lot sooner than people think, but eventually they do happen. 2.5D and 3D packaging has the right balance and an economic tradeoff. So for me, it’s not if it will happen, it’s when.

SE: Any thoughts on moving from silicon to germanium and/or III-V materials in the channels?

Caulfield: We already know how to put different materials together. The real question is that do these materials give you a better power performance than staying with the traditional ways. In this part of the technology cycle, there are still many horses running to see which one is going to win the race.