10nm Fab Challenges

Photomask questions, flow changes, new tools and rising costs are raising new questions about when and how to continue device shrinking.


After a promising start in 2015, the semiconductor equipment industry is currently experiencing a slight lull.

The pause is expected to be short-lived, however. Suppliers of 3D NAND devices are expected to add more fab capacity later this year. And about the same time, foundries are expected to order the first wave of high-volume production tools for 10nm. At 10nm, chipmakers plan to develop a new generation of finFET transistors.

In fact, 10nm is just around the corner. TSMC, for one, hopes to move into 10nm finFET “risk production” by the end of 2015, with volume production slated for late 2016. In general, though, the foundries hope to be in 10nm volume production by 2017.

Needless to say, there are several unknowns and variables. To be sure, 10nm finFET technology will be complex and expensive. And the overall timing for 10nm also remains a question.

“There are changes at 10nm, and some significant ones. But the transistor doesn’t change. It’s still a finFET,” said Shibu Gangadharan, senior director of marketing at Applied Materials. “So how will 10nm go? A lot depends on how 14nm will go. Depending on how quickly the foundries learn the issues with 14nm, that will tell you about 10nm. 10nm by itself is complex. But if you don’t do very well at 14nm, and you don’t learn your lessons, 10nm will certainly be tougher.”

The foundries and their customers are still getting their arms around the issues with 16nm/14nm finFETs. Patterning, Interconnects and process control are arguably the most difficult manufacturing steps at 16nm/14nm.

Chipmakers face the same challenges at 10nm, but some new and different issues are also cropping up. Photomask production, for one, will become more difficult. And the fab flow is more complex with variability on the rise.

The industry will need to get a handle on the 10nm manufacturing issues in order to have more realistic expectations about their schedules. To help the industry get ahead of the curve, Semiconductor Engineering has assembled a list of some of the more challenging process steps at 10nm.

Mask making
Extreme ultraviolet (EUV) lithography missed the market window at 10nm. So, chipmakers will extend 193nm lithography and multiple patterning to 10nm. To deal with the diffraction issues, photomask makers must use various reticle enhancement techniques (RETs) on the mask.

One RET, called optical proximity correction (OPC), is used to modify the mask patterns to improve the printability on the wafer. OPC makes use of assist features, which are getting smaller and more complex at each node.

“The mask shapes got smaller and more complex as we went to 14nm, and it will continue to get smaller and even more complex at 10nm,” said Aki Fujimura, chairman and chief executive of D2S. “Although the main features being written are the same size as before, the process window required is greater. This will increase the demand on OPC to deliver increasingly complex shapes. The minimum SRAF sizes will be smaller than 60nm, and the shapes expected on the mask after the process blur will be less and less orthogonal 1D features, and more and more curvilinear shapes. OPC will output rectilinear shapes, but the jog sizes are small enough that the expected mask shapes will be curvilinear.”

As a result, the write times, and possibly costs, could increase for masks at 10nm. “Inspection becomes also more of a challenge with small complex shapes. CD-SEM becomes more challenging too with non-orthogonal shapes,” Fujimura said. “These issues lead to wafer plane analysis as an increasing trend in order to reduce the burden on the already-loaded AIMS machines. Mask 3D effects become more shape-dependent with the increasing amount of non-orthogonal shapes on the mask. And this will have a significant effect on wafer performance. Wafer plane analysis, particularly with respect to the CD-SEM, will increasingly be 3D.”

All told, mask makers may need to rethink the flow. “Performing simulation-based mask hotspot verification becomes critical in order to avoid mask hotspots from escaping the photomask shop,” he added.

Fab flow and variation
Obviously, the process steps become more complex at each node. “If you look at the cost and technical challenges associated with scaling, it’s very high,” said Jeff Marks, vice president of emerging businesses at Lam Research, in a recent presentation. “There are problems as you go to 10nm and below. You have to manipulate things at the atomic level. The interfaces become more critical.”

With that in mind, chipmakers face a sometimes overlooked challenge—process variation. Variation can be defined as any deviation from an intended goal. “Variability is the death of a fab,” said Thomas Caulfield, senior vice president and general manager of Fab 8 at GlobalFoundries.

The problem with process variation is clear. “That variability concern continues to escalate as you go towards smaller and smaller nodes,” Applied’s Gangadharan said. “It’s not just one particular process. It’s accumulative, because you have process variability that comes from lithography, etch, deposition and every step in the flow.”

So what’s the solution? “That’s why you have very sophisticated techniques around statistical process control, fault detection control, smart sampling and integrated metrology,” GlobalFoundries’ Caulfield said. “All of these things manage and calibrate the variation from your mean-point and make adjustments using feedback information. (Process control has) been around for a while. But every year, it has to be that much tighter and that much more sophisticated.”

Lithography is still the biggest challenge, and most expensive step, in the fab. “We are in 10nm in R&D. For the most part, that’s all multiple patterning. Obviously, the challenge is that you are adding more process steps, cost and cycle times,” said Brian Trafas, chief marketing officer at KLA-Tencor.

From there, chipmakers face several challenges within the lithography cell. “193i uses more multiple patterning than EUV, meaning that edge placement error has to be carefully budgeted, processing costs need to be managed, and EDA/OPC has to properly handle a great deal of pattern splitting and coloring,” said Hamid Zarringhalam, executive vice president at Nikon.

In fact, chipmakers will move to triple or quadruple patterning at 10nm, which will be significantly more difficult to master than double patterning at 16nm/14nm.

For the critical metal layers, chipmakers could go down one of two separate paths at 10nm. In one path, some may implement triple patterning using a litho-etch-litho-etch-litho-etch (LELELE) flow. This is more complex in the fab, but it enables more flexible IC designs.

Still others will embrace self-aligned quadruple patterning (SAQP). This is less complex in the fab flow, but it also has some drawbacks. “What that means is that you are enforcing unidirectional layouts. 1D means that once you enforce restrictions, you can control variability,” said Kelvin Low, senior director of foundry marketing for Samsung. “At the same time, you are making the designers life much more difficult. You have reduced the degree of freedom of laying out your IPs.”

The two approaches, triple patterning and SAQP, have some advantages and disadvantages. “Litho-etch-litho-etch (LELE) is a good way to enable holes, for example,” Applied’s Gangadharan said. “With spacer-based patterns, you are drawing lines. To make holes, you need to make a square. And then you use etch to convert that into a hole. In litho-etch, you can just print a hole. You can’t do that with lines and spacers.”

The problem? “In a brute-force way, you can do litho-etch-litho-etch as many times to get the dimensions you want. But overlay becomes more difficult to manage. And the cost could go through the roof at some point,” Gangadharan said. “Going to spacer-based patterning, in some respects, actually helps with overlay. Spacer-based gives you some relief in line-edge roughness and line-width roughness.”

With SAQP, chipmakers also can move towards a simpler two-step patterning flow using lines and cuts. Patterning the lines is relatively simple. The hard part is to make precise cuts.

LELELE and spacer share one common trait, though. Both are dependent on the etch step, which is the art of removing materials to help shape the design. In finFET production, the hard part is to make fins with consistent heights during the etch process. Imprecise fin patterning could cause variations. “None of the traditional challenges with etch will change at 10nm,” Gangadharan said. “The only thing is that everything tightens up at a certain level.”

In chip production, the backend-of-the-line (BEOL) is where the interconnects are formed within a device. Interconnects—those tiny wiring schemes in devices—are becoming more compact at each node. This, in turn, is causing a degradation in performance and an increase in the resistance-capacitance (RC) delay in chips.

“It’s still a big challenge,” said Sree Kesapragada, global product manager at Applied Materials. “It requires innovation from both the materials and the design side. RC is a function of the line length. That puts the onus on the designers to make sure that at the critical levels, where you are transferring information on power, for example, you don’t exceed a certain length.”

To help solve part of the RC delay problems, chipmakers have introduced new materials in the metallization flow. Starting at 20nm, cobalt replaced tantalum for the liner. Cobalt helps promote the continuity of the copper seed barrier. Meanwhile, tantalum nitride (TaN), which is utilized for the barrier, will extend to 10nm.

Inspection and Metrology
And not to be outdone, wafer inspection and metrology will become more difficult at 10nm. “Every nanometer matters,” KLA-Tencor’s Trafas said. “There are very tight CD and overlay budgets within litho. Today, we are finding there are sources of error in litho and then there are sources of error outside of litho. We need to monitor and measure both of those.”

Then, for finFETs, a given metrology tool must make 12 or more different measurements in three dimensions. “The challenge is how do you measure the depths, trench, sidewall angle, the CD and the resolution of the roughness,” said Keibock Lee, president of Park Systems, a supplier of atomic force microscopy (AFM) tools.

Ultimately, there is no one tool that can handle all metrology needs in the fab. So, chipmakers use a technology called hybrid metrology. In this approach, chipmakers use a mix-and-match of several different tool technologies and then combine the data from each.

  • thakur

    thanks Mark for all the educative articles. They are really nice reads.