Technical Paper Home

AI/ML/DL

• Review of Methods to Design Secure Memristor Computing Systems

  Published on February 27, 2023

• In-Memory Computing: Assessing Multilevel RRAM-Based VMM Operations

  Published on February 26, 2023

• ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)

  Published on February 24, 2023

• HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware

  Published on February 19, 2023

• Review of Tools & Techniques for DL Edge Inference

  Published on February 16, 2023

• New Method Improves Machine Learning Models’ Reliability, With Less Computing Resources (MIT, U. of Florida, IBM Watson)

  Published on February 13, 2023

• Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs

  Published on January 29, 2023

• Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)

  Published on January 29, 2023

• Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)

  Published on January 10, 2023

• MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms

  Published on December 30, 2022
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