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• A RISC-V On-Chip Parallel Power Controller for HPC (ETH Zurich, U. of Bologna)

  Published on February 26, 2023

• Formal Processor Model Providing Secure Speculation For The Constant-Time Policy

  Published on February 24, 2023

• ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)

  Published on February 24, 2023

• HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware

  Published on February 19, 2023

• HBM-Enabled FPGA-Based Graph Processing Accelerator

  Published on February 19, 2023

• Review of Tools & Techniques for DL Edge Inference

  Published on February 16, 2023

• Emulation System for Racetrack Memories Based on FPGA

  Published on February 13, 2023

• Hardware Virtualization Support in the RISC-V CVA6 Core

  Published on February 8, 2023

• Transferring Qubits Directly Between Quantum Computing Microchips (U. of Sussex/ Universal Quantum)

  Published on February 8, 2023

• Side-Channel Attacks Via Cache On the RISC-V Processor Configuration

  Published on January 29, 2023
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