AR/VR glasses; analog IC security; mobile SoC challenges; aerospace/defense security risks; how to talk to your dishwasher; modular cryptography; eIDAS; auto MACsec; multimodal AI MCUs; faster FuSa; AI-defined vehicles.
Optimizing data movement; verification tradeoffs; chiplets, 3D-ICs, and AI; more data, more redundant interconnects; AI shifts from tool agents to development flow agents; future-proofing AI models; optical interconnects; speeding up die-to-die interconnectivity; DAC's real value; stack die stress; RISC-V verification gap; CXL in AI; CSR management.
Cooling options; mask changes; advanced packaging materials; HDFO signal integrity; faster atomistic modeling; ion beam etching for LER; AI energy consumption.
Special report on die-to-die interconnect standards; chiplet development flows; AI accelerators move out from data centers; optimizing analog; UALink; power intent; HBM4.
Special report on three-way race to 3D-ICs; silent data error sources; e-beam inspection at <5nm; financial/manufacturing data; targeted testing for yield limiting defects; Z-axis metrology; AI for test; distributed ATPG; auto security; coaxial test sockets.
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