Signal integrity in chiplets; normalizing AI data; multi-physics definitions; CXL, compression; simulation data management; SMP; vision-enabled devices.
Silent data errors persist in data centers; simulation's role in fab grows; IC equipment communication standards struggle; optimizing DFT; glass substrates; system-level approach in fab; avoiding probe damage.
Auto ecosystem pivots around SDV; med tech flood ahead; system-level auto security; auto OEMs face tech adoption challenges; MACsec, IPsec, and TLS; auto IC reliability; TRNG for auto; edge AI for IIoT.
UCle 2.0 chiplet challenges; more complex chip architectures; verifying custom designs; EDA startup challenges; limits of using AI for data management; livelocks and deadlocks; PCIe over optics; pain points; formal analysis; MCU NoCs; AI infrastructure; DRC; timing variation; voltage droop.
What's next for TSVs; billions for fabs and facilities; power moves closer to ICs; materials challenges and changes; improving GaN architectures; contaminant removal; litho; virtual twins; chiplet ecosystem; med tech.
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