Special report on die-to-die interconnect standards; chiplet development flows; AI accelerators move out from data centers; optimizing analog; UALink; power intent; HBM4.
Special report on three-way race to 3D-ICs; silent data error sources; e-beam inspection at <5nm; financial/manufacturing data; targeted testing for yield limiting defects; Z-axis metrology; AI for test; distributed ATPG; auto security; coaxial test sockets.
Aero IC safety; chiplet cyber threats; AI rewires auto industry; security power requirements grow; complex challenges for chips in space; photonics for data center AI; auto FuSa; SPICE models; eMMC; AI native processing; parallel problems.
AI drives chip re-engineering; improving EDA productivity; analog impact on digital verification; defining AI agents’ goals; SerDes challenges; tape-out failures; regression management; shift-left pattern matching.
Special report on backside power delivery; changes ahead for interposers; chiplet economics; automated packaging; multi-die assemblies; BSPDN channel stress; TCAD and GPUs; PLDC; PMIC heat; FOCoS-CL; ALE simulation.
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