Siemens
The primary responsibility for this position will be to drive the development of workflows to support the physical design planning, layout, and verification of advanced 3D IC designs. These workflows include package floor planning, package/chiplet level functional/ IO planning, interposer/substrate planning, layout, package level connectivity, Logical Equivalence Checking (LEC), package level 3Dstack (DRC/LVS) verification and physical DRC/DFM verification of the package components (excluding the chiplet devices). Additional responsibilities include working with the 3D IC Solutions teams in integrating the other 3D IC workflows into the 3D IC Physical Design workflow.
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