Cadence
Design and develop cycle approximate/Loosly timed C++/SystemC models for Cadence’s IPs like PCIe controller, etc for use in early SW development ,architectural exploration and performance analysis at different levels – subsystem and SoC level.
– Design and develop protocol specific functional models for various Cadence’s interface IPs like PCIe,UCIe,CXL,USB,Ethernet,UFS,DP, etc
– Interact with IP designers and architects to understand various IP design/implementation specification and behavior
– Participate in defining traffic patterns, tools and methodology based on the model to help identify functional issues and performance bottlenecks
– Documentation of design specifications, implementation details, FAQ’s, application notes, etc
For additional details and the most recent updates, hit “Apply for job”
