Strong System Verilog/Verilog RTL design expertise
- Questa/Incisive/VCS simulator experience
- Python/Perl/Tcl scripting experience
- Significant ASIC and/or FPGA design experience
- Ability to learn quickly and work independently
- Solid communication and project management skills
- 5+ years of logic design experience
- BSEE
For additional details and the most recent updates, hit “Apply for job”
