You’ll lead the team generating FPGA designs for interface enablement and validation as well as design for our upcoming platform. This work will be done in conjunction with software and boards engineers. Release material will include engineering flows with a strong focus on engineering efficiency.

Work will include RTL and implementation constraints with high-quality, clear, accurate documentation. Familiarity with RTL and document review processes is desirable. The successful candidate will be responsible for delivery of designs using techniques such as gated clock conversion and synthesizable models to build accurate representations of real-world systems.


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