Cadence
As part of the System Architecture team you will focus on performance by developing and integrating event-driven, cycle-level performance models for various Cadence IPs (including NoC, NPU, Memory Controller, UCIe), building chiplets and chiplet based systems, creating methodologies for architectural exploration, identifying key performance indicators to drive cutting-edge solutions for chiplet based SoCs.
For additional details and the most recent updates, hit “Apply for job”
