Synopsys
The Digital Implementation team is seeking a highly motivated and innovative engineer who be part of the timing team working on timing flows, constraints, analysis & debug of timing issues that will enable physical design activities and will be responsible for physical design implementation of the Mixed-Signal DDR PHY IPs in various cutting edge process technologies. In this role you will work on a variety of advanced DDR PHY developments including the latest standards in LP5x and DDR5. The position offers an excellent opportunity to work with an expert team of digital and mixed-signal engineers.
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