As a Lead or Principal Physical Design Engineer, the candidate will be reporting to the Sr. Director, Engineering and is a Full-Time position. Successful applicant will have highly visible role in product definition/design across Rambus sites.

Ownership of Analog/Mixed designs at chip and/or block level
Define optimal architectures to achieve competitive product specifications.
Perform partition synthesis and physical implementation steps (e.g. synthesis, floor-planning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Characterize Analog IP with tools such as Nanotime/Silicon Smart etc.
Develop/improve physical design methodologies and automation scripts for various implementation steps
Collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop


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