Siemens

Responsible for interfacing with mid-level customers, engineers, and managers to develop or enhance complex computer-aided engineering design or manufacturing processes; Utilizing design and tooling tasks involving multiple design environments; Communicating software problems to product development; Honing verification methodologies related to RTL design verification and Gate level simulation aspects; Developing in-depth technical papers and presentations to customers; Collaborating with internal research and development engineering teams to define, prototype, evaluate, and test new Questasim features in context of complex IC design and verification flows; Completing files enhancement and defect reports to address product gaps and defects; Developing test cases for the quality assurance group via testing of user scenarios; Driving product adoption; Building and delivering in-depth technical presentations, training materials, white papers, contributed articles, and application notes; Collaborating with customers and stakeholders such as regional application engineers, global support engineers, and marketing; Collecting customer feedback about product applicability and requirements; Debugging System Verilog RTL, UVM, and SVA issues.

 

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