Siemens
The Tessent team is responsible for developing and providing DFT solutions involving test IPs that improve the overall testability of a design. These test IPs are delivered and treated as any regular IP that must be integrated into customer designs. As the complexity of designs grows along with shrinking design cycles, there is a trend across the industry to push much of the DFT analysis, insertion, and integration of the DFT IPs in RTL. The successful candidate should have very good knowledge of Tcl/Python programming, digital circuit design, and design implementation flows with particular emphasis on delay constraints, static timing analysis, and timing optimization techniques. The candidate must also be conversant with hardware-description languages such as System Verilog and VHDL. The candidate is expected to become an expert on Tessent IPs and will be actively guiding our customers to integrate the test instruments into their designs.
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