SPE Analog Engineer

The candidate will be part of Rambus Memory Interface Chips BU’s design group responsible for specifying, architecting, executing and productizing leading edge memory interface buffer chips for DDR5, DDR6 and beyond.

• Owner and domain expert of analog and mixed signal designs at chip and block level
• Architect, design, simulate and characterize high-performance and low-power high-speed circuits, especially PLL, DLL, Phase Interpolators, Duty-cycle correction, and other clocking related elements.
• Modeling of chip and block level at various levels of detail for design tradeoff analysis and voltage and timing budgeting
• Supervise analog layout engineering to ensure attention to detail on high performance analog layout for critical blocks
• Work closely with cross-functional teams across different geographies and time zones to ensure engagement and execution
• Other responsibilities include layout supervision, design documentation, customer interaction and post silicon activity support

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