As a Senior Princial Verification Engineer, the candidate will be reporting to the Senior Director Analog Engineer and is a Full Time position.
Responsibilities
- Create digital verification plans using datasheets, inputs from engineers/customers, and working closely with system and design engineers.
- Implement digital test-benches in SystemVerilog and UVM to apply constrained random stimulus and checks.
- Implement Systemverilog Assertions (SVA) to check digital DUT behavior.
- Track bugs, functional coverage, and RTL code coverage
- Work with design and systems teams to close bugs as they arise.
- Work in a dynamic and interdisciplinary R&D group contributing to flow and methodology development
- Mentor junior designers
For additional details and the most recent updates, hit “Apply for job”
