Responsibilities:
- As a creative verification engineer with a knowledge of SoC integration verification, SoC scenario verification, SoC performance verification, CHI/PCIe/CXL, DDRx/LPDDRx integration verification in SoC RTL.
- Your key responsibilities will include writing test plans, defining test methodologies, developing SystemVerilog/Verilog testbenches and tests, and debugging of test failures and issues.
- Working with project management and leads on planning tasks, setting schedules, and quality checkpoints.
- Collaborate with engineers from other teams including architecture, design, implementation, modelling, performance analysis, silicon validation, FPGA and board development
- Staff Engineers are also encouraged to mentor junior members
For additional details and the most recent updates, hit “Apply for job”
