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• Review of Methods to Design Secure Memristor Computing Systems

  Published on February 27, 2023

• Security-Aware Compiler-Assisted Countermeasure to Mitigate Fault Attacks on RISC-V

  Published on February 26, 2023

• Formal Processor Model Providing Secure Speculation For The Constant-Time Policy

  Published on February 24, 2023

• HW-SW Co-Design Solution For Building Side-Channel-Protected ML Hardware

  Published on February 19, 2023

• Detecting Hardware Trojans In a RISC-V Core’s Post-Layout Phase

  Published on February 8, 2023

• RSFQ Logic Based Logic Locking Technique For Immunizing Against SAT-Based Attacks

  Published on February 8, 2023

• Side-Channel Attacks Via Cache On the RISC-V Processor Configuration

  Published on January 29, 2023

• Mitigating Silent Data Corruptions in High Performance Computing

  Published on January 29, 2023

• Automotive E/E Architectures with Safety Related Availability (SaRa) Requirements For Highly Autonomous Driving

  Published on January 29, 2023

• Hardware Trojan Detection Case Study Based on 4 Different ICs Manufactured in Progressively Smaller CMOS Process Technologies

  Published on January 11, 2023
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