Technical Paper Home

AI/ML/DL

• New Method Improves Machine Learning Models’ Reliability, With Less Computing Resources (MIT, U. of Florida, IBM Watson)

  Published on February 13, 2023

• Heterogeneous Multi-Core HW Architectures With Fine-Grained Scheduling of Layer-Fused DNNs

  Published on January 29, 2023

• Efficiently Process Large RM Datasets In Underlying Memory Pool, Disaggregated Over CXL (KAIST)

  Published on January 29, 2023

• Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)

  Published on January 10, 2023

• MTJ-based Circuits Provide Low-Cost, Energy Efficient Solution For Future Hardware Implementation in SC Algorithms

  Published on December 30, 2022

• Neural Architecture & Hardware Accelerator Co-Design Framework (Princeton/ Stanford)

  Published on December 12, 2022

• 2D-Materials-Based Electronic Circuits (KAUST and TSMC)

  Published on December 6, 2022

• Optimizing Hardware Capacity, Utilizing Automatic Differentiation to Efficiently Compute Derivatives in Parallel Programming Models

  Published on November 30, 2022

• Profile-Guided HW/SW Mechanism To Efficiently Reduce Branch Mispredictions In Data Center Applications (Best Paper Award)

  Published on November 17, 2022

• Memory and Energy-Efficient Batch Normalization Hardware

  Published on November 17, 2022
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