Originally Zetatech Inc.
Vantage Analysis Systems created an integrated toolset that operates with VHDL’s common data format for the entire design sequence. The Vantage Spreadsheet eliminated four steps used by many other simulation systems to expand the design hierarchy and translate net-list formats. An IEEE 1076 compiler at the front end of the simulation environment performs a syntax and semantic analysis of a VHDL source file and produces an intermediate data format simulation. Consequently, with design changes that require long recompilations using simulation net-list formats based on other languages, Vantage Spreadsheet proceeds directly to simulation and display after the schematic check. The second major time-saving feature is concurrent processing of schematic changes, simulator updating, simulation, and displayed results.
