Peter Flake is the Chief Scientist at Imperas, Inc., a start-up company focused on multi-processor design solutions. In 1998, he co-founded and became the Chief Technology Officer at Co-Design Automation, where he architected the Superlog language, the basis of today’s SystemVerilog standard. He became a Scientist at Synopsys in 2003 after the acquisition of Co-Design by that company. During the 1980’s he was the language architect and project leader of HILO, the first commercial hardware description language (HDL) based simulation, fault simulation and timing analysis system, while at Brunel University in Uxbridge, U.K., and then at GenRad, Inc. Peter Flake holds a Master of Arts degree from Cambridge University in the U.K. and has made numerous conference presentations on the subject of HDLs.
