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• Analog In-Memory Computing: Fast Deep NN Training (IBM Research)

  Published on September 10, 2024

• Scalable Chiplet System for LLM Training, Finetuning and Reduced DRAM Accesses (Tsinghua University)

  Published on September 4, 2024

• DL Compiler for Efficiently Utilizing Inter-Core Connected AI Chips (UIUC, Microsoft)

  Published on August 28, 2024

• GPU Microarchitecture Integrating Dedicated Matrix Units At The Cluster Level (UC Berkeley)

  Published on August 27, 2024

• Benefits Of The Ultra-Low Leakage Currents from IGZO TFTs For Neuromorphic Applications

  Published on August 27, 2024

• Characterizing Three Supercomputers: Multi-GPU Interconnect Performance

  Published on August 27, 2024

• Survey of Energy Efficient PIM Processors

  Published on August 1, 2024

• Co-optimizing HW Architecture, Memory Footprint, Device Placement And Per-Chip Operator Scheduling (Georgia Tech, Microsoft)

  Published on July 28, 2024

• CHERI RISC-V: HW Extension for Conditional Capabilities

  Published on July 28, 2024

• Using Diffusion Models to Generate Chip Placements (UC Berkeley)

  Published on July 27, 2024
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